2022年FPGA控制LED汉字滚动显示器设计方案.docx

精品学习资源封面欢迎下载精品学习资源作者： PanHongliang仅供个人学习基于 FPGA 把握的 LED 汉字滚动显示器设计2 硬件原理图整个电路由五大部分组成：时钟计数模块GEL_CLK，储备汉字字模的ROM 模块ROMZI ，数据支配器模块MUX ，移位模块 YW 及显示模块XIANSH-I ；时钟计数模块用于欢迎下载精品学习资源产生整个电路所需要的时钟及其对时钟的计数值，例如：移位时钟CLK YW，移位计数器CNT YW，字计数器 CNT WORD ，显示扫描计数器 CNT SM；ROMZI 模块是由 Qualtus 中的 LPM 1PORT ROM 定制成，用来储备 8 个待显示的汉字； MUX 模块用于在扫描时钟及扫描计数器的作用下，从 ROM 中读出一个汉字的 8 个行字模信息，送给移位模块 YW，YW 模块在移位时钟及移位计数器作用下，依据SELECT信号选择对读出的字模信息，进行相应的移位 左移、右移、上移、下移 后，最终送显示模块DISP 驱动 LED 点阵显示汉字；原理图如图 2 所示；3 2 ROMZI 模块利用 LPM 参数化模块库中单口ROM，利用 Qualtus 中的 MegaWizard Plug-In Manager 定制而成，定制前第一要制作LPM ROM 初始化文件，其中储备待显示汉字的字模数据，然后依据LPM MegaWizardPlug-In Manager的向导提示，结合设计要求进行定制；图 3 为所定制 ROM 中的初始化汉字 “元旦生日兴奋欢快”的字型码；数据支配模块MUX 要求能在 8 个时钟作用下，从ROM 中读出一行 一个汉字的 8 个字型码 分别送到数据支配器中的WLl WL8 输出端；图 4 为数据支配模块在扫描时钟作用下读取的字模数据，比较图 3 和图 4 可知，仿真结果正确，能中意题目要求；3 3 移位模块 YW移位模块 YW 是整个设计的核心，行扫描实现左移，是通过每来一个移位时钟，将每一行的字模按位左移一位，扫描时钟到来时送出移位后的新字模；通过8 次移位，可将一个汉字移出点阵平面，按类似的道理，也可以将一个汉字经8 次移位后移进点阵平面；本例 图 2 中， CNT YW 为移位时钟的计数值，以WLl WL8 为欲显示汉字的原始字模， L10 L80 为移位后从列上送出的8 行显示字模信息，LLl LL8 为 8 个原始字模信息未送出位的暂存信号；设计中需要16 个移位时钟，通过前8 个时钟将 WLl WL8 字模移进 LED点阵平面，再经后8 个时钟，将汉字又一位一位地移出；移位设计参考文献中有关移位寄存器的设计，分计数值为“0000"和非 "0000" 两部分处理，对第一行字模的处理为：其他行可按相同方法处理，具体参见如下的程序：library IEEE ；use IEEE.std_logic_1164.all ；use ieee.std_logic_arith.all ；use ieee.std_logic_unsigned.all ；欢迎下载精品学习资源entity memtest is port rst: in std_logic ；clk: in std_logic ；den: in std_logic ；-serial input enable rxd: in std_logic ；-serial input data outen : in std_logic ；- output data request rdmem : out std_logic ；-read memory wrmem : out std_logic ；- write memorycsmem : out std_logic ；- chip enable memorymemdata: inout std_logic_vector7 downto 0；- memory data interface memaddr: out std_logic_vector2 downto 0 ； - memory address dataout: out std_logic_vector7 downto 0 ；-data outputdataclkout: out std_logic -data output sync clk；end memtest；architecture behav of memtest isconstant s0 :std_logic_vector2 downto 0:= "001"；constant s1 :std_logic_vector2 downto 0:= "010"；constant s2 :std_logic_vector2 downto 0:= "100"；signal ss: std_logic_vector2 downto 0 ；signal rdmemaddr,wrmemaddr: std_logic_vector2 downto 0；signal rxdcnt: std_logic_vector3 downto 0；signal rdmemdata, wrmemdata :std_logic_vector7 downto 0；signal wrmem_s, wrrdy, dataclkout_s :std_logic；beginprocessrst,clk beginif rst = '0' thenwrmemdata <= others =>'0' ；elsif clk'event and clk = '1' then if den = '1' then欢迎下载精品学习资源wrmemdata7 <= wrmemdata6 ；wrmemdata6 <= wrmemdata5 ；wrmemdata5 <= wrmemdata4 ；wrmemdata4 <= wrmemdata3 ；wrmemdata3 <= wrmemdata2 ；wrmemdata2 <= wrmemdata1 ；wrmemdata1 <= wrmemdata0 ；欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；wrmemdata0 <= rxd ；欢迎下载精品学习资源if rst = '0' thenrxdcnt <= others =>'0' ；elsif clk'event and clk = '1' then if den = '1' thenif rxdcnt = 9 thenrxdcnt <= rxdcnt ；elserxdcnt <= rxdcnt +1 ；end if ；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；rxdcnt <= others =>'0' ；欢迎下载精品学习资源if rst = '0' thenss <= s0；elsif clk'event and clk = '1' then欢迎下载精品学习资源case ss iswhen s0 =>if wrrdy = '1' thenss <= s1；elsif outen = '1' thenss <= s2；end if ；when s1 =>ss <= s0；when s2 =>ss <= s0；when others =>ss <= s0；end case；end if ；end process；processrst,clk beginif rst = '0' thenwrrdy <= '0' ；elsif clk'event and clk = '1' then if ss = s1 thenwrrdy <= '0' ；elseif rxdcnt = 8 thenwrrdy <= '1' ；欢迎下载精品学习资源elseend if ；wrrdy <= '0' ；欢迎下载精品学习资源欢迎下载精品学习资源end if ；end process；end if ；欢迎下载精品学习资源wrmem_s <= '0' when ss = s1 else '1'；rdmem <= '0' when ss = s2 else '1'；csmem <= '1' when ss = s1 or ss = s2 else '0'；processrst,clk beginif rst = '0' thendataclkout_s <= '0' ；elsif clk'event and clk = '1' thenif ss = s2 thendataclkout_s <= '1' ；elsedataclkout_s <= '0' ；end if ；end if ；end process；processclk beginif clk'event and clk = '1' thendataclkout <= dataclkout_s ；end if ；end process；processrst,clkbeginif rst = '0' thendataout <= others =>'0' ；elsif clk'event and clk = '1' thenif ss = s2 thendataout <= rdmemdata；end if ；end if ；end process；欢迎下载精品学习资源processrst,clk beginif rst = '0' thenwrmemaddr <= others =>'0' ；elsif clk'event and clk = '1' then if ss = s1 then欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；wrmemaddr <= wrmemaddr +1 ；欢迎下载精品学习资源if rst = '0' thenrdmemaddr <= others =>'0' ；elsif clk'event and clk = '1' then if ss = s2 thenrdmemaddr <= rdmemaddr +1 ；end if ；end if ；end process；memaddr <= wrmemaddr when wrmem_s = '0' else rdmemaddr ；memdata <= wrmemdata when wrmem_s = '0' else "ZZZZZZZZ"；rdmemdata <= memdata；wrmem <= wrmem_s ；end behav；library IEEE ；use IEEE.std_logic_1164.all ；欢迎下载精品学习资源use ieee.std_logic_arith.all ；use ieee.std_logic_unsigned.all ；entity states is欢迎下载精品学习资源port ；rst : in std_logic ；clk : in std_logic ；nscar: in std_logic ；ewcar: in std_logic ；nsred: out std_logic ；nsgreen: out std_logic ；nsyellow: out std_logic ；ewred: out std_logic ；ewgreen: out std_logic ；ewyellow: out std_logic欢迎下载精品学习资源end states；architecture behav of states isconstant s0 :std_logic_vector1 downto 0:= "00"；- ewgreen constant s1 :std_logic_vector1 downto 0:= "01"；constant s2 :std_logic_vector1 downto 0:= "11"；- nsgreenconstant s3 :std_logic_vector1 downto 0:= "10"；signal ss: std_logic_vector1 downto 0 ；signal tm60s,tm40s :std_logic_vector5 downto 0；signal tm3s :std_logic_vector1 downto 0；signal entm60s,entm40s,entm3s,tm60soc,tm40soc,tm3soc :std_logic ；beginprocessrst,clk beginif rst = '0' thenss <= s0；elsif clk'event and clk = '1' then case ss is欢迎下载精品学习资源when s0 =>if nscar = '1' thenif ewcar = '1' thenif tm60soc = '1' thenss <= s1；end if；else欢迎下载精品学习资源end if ；when s1 =>end if ；ss <= s1；欢迎下载精品学习资源if tm3soc = '1' thenss <= s2；end if ；when s2 =>if nscar = '1' thenif ewcar = '1' thenif tm40soc = '1' then欢迎下载精品学习资源end if ；end if；ss <= s3；欢迎下载精品学习资源elsess <= s3；end if ；when s3 =>if tm3soc = '1' thenss <= s0；end if ；when others =>ss <= s0；end case；end if ；欢迎下载精品学习资源end process；processrst,clk beginif rst = '0' thenentm60s <= '0'； elsif clk'event and clk = '1' thenif ss = s0 thenentm60s <= '1'；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；entm60s <= '0'；欢迎下载精品学习资源if rst = '0' thenentm40s <= '0'； elsif clk'event and clk = '1' thenif ss = s2 thenentm40s <= '1'；elseentm40s <= '0'；end if ；end if ；end process；processrst,clkbeginif rst = '0' thenentm3s <= '0'；elsif clk'event and clk = '1' thenif ss = s1 or ss = s3 then欢迎下载精品学习资源entm3s <= '1'；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；entm3s <= '0'；欢迎下载精品学习资源if rst = '0' thentm60s <= B"000000" ；elsif clk'event and clk = '1' then if entm60s = '1' thenif tm60s = 59 thentm60s <= B"000000" ；elsetm60s <= tm60s + 1 ；end if ；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；tm60s <= B"000000" ；欢迎下载精品学习资源if rst = '0' thentm40s <= B"000000" ；elsif clk'event and clk = '1' then if entm40s = '1' thenif tm40s = 39 thentm40s <= B"000000" ；elsetm40s <= tm40s + 1 ；欢迎下载精品学习资源end if ；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；tm40s <= B"000000" ；欢迎下载精品学习资源if rst = '0' thentm3s <= B"00" ；elsif clk'event and clk = '1' then if entm3s = '1' thenif tm3s = 2 thentm3s <= B"00" ；elsetm3s <= tm3s + 1 ；end if ；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；tm3s <= B"00" ；欢迎下载精品学习资源if rst = '0' thentm60soc <= '0' ；elsif clk'event and clk = '1' thenif tm60s = 59 thentm60soc <= '1' ；elsetm60soc <= '0' ；end if ；欢迎下载精品学习资源end if ；end process；processrst,clkbeginif rst = '0' thentm40soc <= '0' ；elsif clk'event and clk = '1' thenif tm40s = 39 thentm40soc <= '1' ；else欢迎下载精品学习资源end if ；end process；processrst,clkbeginend if ；tm40soc <= '0' ；欢迎下载精品学习资源if rst = '0' thentm3soc <= '0'；elsif clk'event and clk = '1' then if tm3s = 2 thentm3soc <= '1'；elsetm3soc <= '0'；end if ；end if ；end process；processrst,clkbeginif rst = '0' thennsred <= '1'；nsgreen <= '0'；nsyellow <= '0' ；欢迎下载精品学习资源ewred <= '0' ；ewgreen <= '1'；ewyellow <= '0' ；elsif clk'event and clk = '1' then case ss iswhen s0 =>nsred <= '1'；nsgreen <= '0'；nsyellow <= '0' ；ewred <= '0' ；ewgreen <= '1'；ewyellow <= '0' ；when s1 =>nsred <= '0'；nsgreen <= '0'；nsyellow <= '1' ；ewred <= '0' ；ewgreen <= '0'；ewyellow <= '1' ；when s2 =>nsred <= '0'；nsgreen <= '1'；nsyellow <= '0' ；ewred <= '1' ；ewgreen <= '0'；ewyellow <= '0' ；when s3 =>nsred <= '0'；nsgreen <= '0'；nsyellow <= '1' ；ewred <= '0' ；ewgreen <= '0'；欢迎下载精品学习资源ewyellow <= '1' ；when others =>欢迎下载精品学习资源end if ；end process；end behav；end case；版权申明欢迎下载精品学习资源本文部分内容，包括文字、图片、以及设计等在网上搜集整理；版权为潘宏亮个人全部This article includes some parts, including text, pictures, and design. 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