具有左转功能的交通灯(共10页).doc
精选优质文档-倾情为你奉上交通灯系统框图：根据设计要求和系统所具有的功能，并参考相关的文献资料，经行方案设计，可以画出如下图所示的交通信号灯控制器的系统框图。 CLK 时钟分频模块 交通灯控制及计时模块 50MHZ 扫描显示译码模块 50MHZ 1HZ 50MHZ 数码管及LED信号 数码管段码 数码管位码 LED显示系统的状态转换图如下所示：交通灯设计过程中总共只需要八个状态即可完，设置A为主干道，B为支干道，则B路的红灯时间要长于A路10秒，而绿灯时间则要缩短10s,详细情况见下状态图。系统模块图如下所示：在用QUARTUS综合后可得到详细的原理图，详细情况见下：简单仿真图：用Modelsim进行仿真，由于50MHZ分频后，仿真图上状态转换很难观测，于是降低分频系数，便于观察从而得到近似的仿真结果，在下板子的过程中只需要将分频系数改回原来的50MHZ 分频即可。引脚分配：使用ALTERA的DE2-70来模拟交通灯过程，将引脚绑定，具体引脚分配详见下图：交通灯实物模拟图：将编译好的程序下载如DE2-70，模拟后得到如下图：交通灯代码：初始化模块：module init_mod(reset,ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft); input reset; output7:0 ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft; reg7:0 ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft; always(reset) /? if(!reset) begin ared<=8'b; /55s ayellow<=8'b; /5s agreen<=8'b; /40s aleft<=8'b; /15s bred<=8'b; /65s byellow<=8'b; /5s bgreen<=8'b; /30s bleft<=8'b; /15s endendmodule分频模块：module div_clk(CLK,reset,CLK_1HZ); input CLK,reset; output CLK_1HZ; reg CLK_1HZ; reg25:0count; always(posedge CLK or negedge reset) begin if(!reset) begin CLK_1HZ=0; count=0; end else if(count < 26'd) /?0.5s? begin count=count+1; /? end else begin count=0; /? CLK_1HZ=CLK_1HZ; /?1s end end endmoduleA方向控制计数模块：module traffic_A(CLK_1HZ,reset,ared,ayellow,agreen,aleft,lampa,numa); output3:0 lampa; output7:0 numa; input CLK_1HZ; input reset; input7:0 ared,ayellow,agreen,aleft; reg7:0 numa; /? reg tempa; /? reg2:0 counta; /? reg3:0 lampa; always(posedge CLK_1HZ or negedge reset) / begin if(!reset) /? begin lampa<=4'b1000; counta<=0; tempa<=0; numa<=0; endelseif(!tempa) /? begin tempa<=1'b1; /? case(counta) /? 0:begin numa<=agreen;lampa<=4'b0100;counta<=1;end /? 1:begin numa<=ayellow;lampa<=4'b0010;counta<=2;end /? 2:begin numa<=aleft;lampa<=4'b0001;counta<=3;end /? 3:begin numa<=ayellow;lampa<=4'b0010;counta<=4;end /? 4:begin numa<=ared;lampa<=4'b1000;counta<=0;end /? default: lampa<=4'b1000; /? endcase end else /? begin if(numa>1) if(numa3:0=0) /?0? begin numa3:0<=4'b1001; /?9 numa7:4<=numa7:4-1; /?1 end else numa3:0<=numa3:0-1; /?1 if(numa=2) tempa<=0; end end endmoduleB方向控制计数模块：module traffic_B(CLK_1HZ,reset,bred,byellow,bgreen,bleft,lampb,numb); output3:0 lampb; output7:0 numb; input CLK_1HZ; input reset; input7:0 bred,byellow,bgreen,bleft; reg7:0 numb; /? reg tempb; /? reg2:0 countb; /? reg3:0 lampb; always(posedge CLK_1HZ or negedge reset) begin if(!reset) /? begin lampb<=4'b1000; countb<=0; tempb<=0; numb<=0; endelseif(!tempb) /? begin tempb<=1; /? case(countb) /? 0:begin numb<=bred;lampb<=4'b1000;countb<=1;end /? 1:begin numb<=bgreen;lampb<=4'b0100;countb<=2;end /? 2:beginnumb<=byellow;lampb<=4'b0010;countb<=3;end 3:begin numb<=bleft;lampb<=4'b0001;countb<=4;end /? 4:beginnumb<=byellow;lampb<=4'b0010;countb<=0;end default lampb<=4'b1000; endcase end else /? begin if(numb>1) if(numb3:0=0) /?0? begin numb3:0<=4'b1001 ; /?9 numb7:4<=numb7:4-1; /?1 end else numb3:0<=numb3:0-1; /?1 if(numb=2) tempb<=0; end end endmodule显示模块：module display(in4,out8); output7:0out8; input3:0in4; reg7:0out8; always(in4) /? begincase(in4) 4'h0:out8=8'hc0; 4'h1:out8=8'hf9; 4'h2:out8=8'ha4; 4'h3:out8=8'hb0; 4'h4:out8=8'h99; 4'h5:out8=8'h92; 4'h6:out8=8'h82; 4'h7:out8=8'hf8; 4'h8:out8=8'h80; 4'h9:out8=8'h90; 4'ha:out8=8'h88; 4'hb:out8=8'h83; 4'hc:out8=8'hc6; 4'hd:out8=8'ha1; 4'he:out8=8'h86; 4'hf:out8=8'h8e; endcaseendendmodule顶层模块：module traffic(CLK,reset,lampa,lampb,out8_a_h,out8_a_l,out8_b_h,out8_b_l); input CLK; input reset; output3:0lampa,lampb; output7:0out8_a_h,out8_a_l,out8_b_h,out8_b_l; wire7:0ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft; wire CLK_1HZ; wire7:0numa_m,numb_m; /* ? */init_modQ1(.reset(reset),.ared(ared),.ayellow(ayellow),.agreen(agreen),.aleft(aleft),.bred(bred),.byellow(byellow),.bgreen(bgreen),.bleft(bleft); div_clk Q2(.CLK(CLK),.CLK_1HZ(CLK_1HZ),.reset(reset); traffic_A Q3(.CLK_1HZ(CLK_1HZ),.reset(reset),.ared(ared),.ayellow(ayellow),.agreen(agreen),.aleft(aleft),.lampa(lampa),.numa(numa_m); traffic_B Q4(.CLK_1HZ(CLK_1HZ),.reset(reset),.bred(bred),.byellow(byellow),.bgreen(bgreen),.bleft(bleft),.lampb(lampb),.numb(numb_m); /B?display Q5(.in4(numa_m7:4),.out8(out8_a_h); /4?A?B?display Q6(.in4(numa_m3:0),.out8(out8_a_l); display Q7(.in4(numb_m7:4),.out8(out8_b_h); display Q8(.in4(numb_m3:0),.out8(out8_b_l); endmodule 专心-专注-专业
