FPGA技术课程作业.docx
精选优质文档-倾情为你奉上1. 分析test2.v程序,完成下列各题：1） 完成程序填空。2） 画出该代码综合后的电路图。module test2 (clk,reset,in1,in2,in3,out1,out2 );input clk,reset;input in1,in2, in3 ;output out1,out2;reg out1,out2; integer temp1,temp2;always (posedge clk or posedge reset) if(reset) begin temp1 <= 0; temp2 <= 0;end else begin temp1 <= in1 & in2;temp2 <= in2 | in3;endalways (posedge clk) begin out1 <= temp1 & temp2; out2 <= temp1 in3; endendmodule 2、分析test1.v程序，完成下列题目：1） 完成程序填空。2） 根据图一所画出的输入激励波形，编写测试文件，仿真截图在0到900ns时间区间里输出端口的输出波形。module test1(data_1,data_2,data_3,data_out1,data_out2 );input data_1,data_2,data_3;output data_out1,data_out2; task writeburst ;input a,b; integer c; c = a + b;endtaskreg data_out1,data_out2;always (data_1 or data_2 or 3 )begin write(data_1,data_2,data_out1); write(data_2,data_3,data_out2);endendmodule图一3. 根据下面的Verilog HDL代码，画出综合后的电路图。module test12(out,clk,in1,in2,in3,in4);input clk;input in1,in2,in3,in4;output out;reg out;reg temp1,temp2;always (posedge clk)begin temp1 <= in1 & in2; temp2 <= temp1 | in3; out <= temp2 | in4;endendmodule4. 根据图1所示的原理图写出相应的Verilog HDL程序，其中DFF模块是上升沿触发的触发器，编写相应的测试程序，在ISE软件中完成仿真，对仿真波形图进行截图。图二程序：module my_moduke (clk,xin,out); input clk,xin; output out; reg out; reg temp; always(posedge clk) begin temp<=xin|out; end always(posedge clk) begin out=temp; endendmodule激励文件：initialbeginclk=0;forever #30 clk=clk;endinitial begin/ Initialize Inputsxin = 0;forever #300 xin=xin;end仿真：5. 用Verilog HDL设计一个四分频电路，在ISE软件中完成仿真，对仿真波形图进行截图。1）输入信号：clk- 输入时钟 reset-同步复位信号，当reset=1b1时，系统输出置零，当reset=1b0时，系统正常工作。 2）输出信号：clk_out -输出信号，其频率是输入时钟的四分之一module D_4div(clkin,reset_n,clkout);input clkin,reset_n; output clkout; wire in1,in2,clkin_2;reg out; reg clkout_1; assign in1=clkout_1;assign clkin_2=clkout_1; assign in2=out; assign clkout=out;always(posedge clkin) /由第一个D触发器构成的2分频程序；beginif(!reset_n) begin out<=0; clkout_1<=0; end else clkout_1<=in1;endalways(posedge clkin_2) /由第二个D触发器构成的2分频程序时钟输入为上面的输出；begin if(!reset_n) out<=0; else out<=in2;endendmodule6.设计一个带有异步复位控制端和时钟使能控制端的10进制计数器。module Counter(clk,clk_key,clr,ena,cout,sel,seg);input clk,clk_key,clr,ena; output cout; output 7:0sel,seg;assign sel=8'hf0;wire clk_k;debounce_module U0 (.CLK(clk),.RSTn(clr),.Pin_In(clk_key),.Pin_Out(clk_k);wire 3:0sum;count U1(.clk(clk),.clk_k(clk_k),.clr(clr),.ena(ena),.cout(cout),.sum(sum);tube U2(.clk(clk),.sum(sum),.seg(seg);endmodule计数模块module count(clk,clk_k,clr,ena,cout,sum);input clk,clk_k,clr,ena; output cout; output 3:0sum;reg cout; reg 3:0sum; reg a,b;always(posedge clk)begin a<=clk_k； b<=a;endwire key_posedge=(b&a) ? 1'b1 :1'b0;always(posedge clk)begin if(clr) begin cout <=0； sum <=0; end else if(key_posedge & ena) begin if(sum<4'd9) begin sum<=sum+1'b1; cout<=0; end else begin cout<=1; sum<=0; end end elsebegin cout<=cout； sum<=sum; endendendmodule数码管module tube(clk,sum,seg);input clk; input 3:0sum; output 7:0seg; reg 7:0seg;always(posedge clk)begincase(sum)4'd0:seg<=8'hc0; 4'd1:seg<=8'hf9; 4'd2:seg<=8'ha4; 4'd3:seg<=8'hb0;4'd4:seg<=8'h99; 4'd5:seg<=8'h92; 4'd6:seg<=8'h82; 4'd7:seg<=8'hf8;4'd8:seg<=8'h80; 4'd9:seg<=8'h90; default:seg<=8'h00;Endcaseendendmodule7. 第八章内容将运用在实验二中，请对第八章进行自学，并针对实验二的chipscope下载测试进行预习。专心-专注-专业
