乒乓球比赛游戏机设计总结报告.doc

【精品文档】如有侵权，请联系网站删除，仅供学习与交流乒乓球比赛游戏机设计总结报告.精品文档.现代电子与系统设计总结报告项目名称： 乒乓球比赛游戏机班 级： 物科院1005姓 名： 周* 沈*学 号： 071005* 071005*指导老师： 倪*提交日期： 2012/12/23封面1一、设计要求3二、设计的具体实现.31、系统框图.32、甲乙方得分显示模块.43、加减计数模块.64、译码模块.85、控制模块.96、核心问题.12三、结果分析.15四、附件161、完整电路图.162、各个自制元件的VHDL程序.16一、设计要求设计一个乒乓球比赛游戏机（1）设计一个由甲乙双方参加，有裁判的三人乒乓球游戏机；（2）用8个（或更多个）LED排成一条直线，以中点为界，两边各代表参赛双方的位置，期中一只点亮的LED指示球的当前位置，点亮的LED依次从左到右，或从右到左，其移动的速度应能调节；（3）当“球”（点亮的那支LED）运动到某方的最后一位时，参赛者应能果断地按下位于自己一方的按钮开关，即表示启动球拍击球，若击中则球向相反方向移动，若未击中，球掉出桌外，则对方得一分；（4）设计自动计分电路，甲乙双方各用两位数码管进行计分显示，每记满11分为1局；（5）甲乙双方各设一个发光二极管表示拥有发球权，每隔2次自动交换发球权，拥有发球权的一方发球才有效；（6）其他。二、设计的具体实现1、系统框图此系统框图分为控制模块，加/减计数模块，译码显示模块和甲乙方得分显示模块。2、甲乙方得分显示模块甲乙双方各用两位数码管进行计分显示，通过控制模块加以控制。甲乙得分的计数：图形：VHDL语言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jifen ISPORT(reset : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jifen;ARCHITECTURE jifen_architecture OF jifen ISBEGIN process(clk,reset) begin if(reset='0') then q<="0000" elsif(clk'event and clk='1') then if(q="1011") then q<="1011" else q<=q+1; end if; end if; end process;END jifen_architecture;甲乙得分的显示：图形：VHDL语言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY xianshi ISPORT(a : IN STD_LOGIC_VECTOR(3 downto 0);y1 : OUT STD_LOGIC_VECTOR(6 downto 0);y0 : OUT STD_LOGIC_VECTOR(6 downto 0);END xianshi;ARCHITECTURE xianshi_architecture OF xianshi ISBEGIN process(a) begin case a is when "0000" => y1<="1111110"y0<="1111110" when "0001" => y1<="1111110"y0<="0110000" when "0010" => y1<="1111110"y0<="1101101" when "0011" => y1<="1111110"y0<="1111001" when "0100" => y1<="1111110"y0<="0110011" when "0101" => y1<="1111110"y0<="1011011" when "0110" => y1<="1111110"y0<="1011111" when "0111" => y1<="1111110"y0<="1110000" when "1000" => y1<="1111110"y0<="1111111" when "1001" => y1<="1111110"y0<="1111011" when "1010" => y1<="0110000"y0<="1111110" when OTHERS => y1<="0110000"y0<="0110000" end case; end process; END xianshi_architecture;甲乙方得分显示模块图形输入为：3、加减计数模块通过的取值实现加或者减的计数。图形：说明：ud=1时，计数器进行减计数；ud=0时，计数器进行加计数；s=0时，计数器正常工作；s=1时，计数器停止工作；reset=1时，计数器正常计数；reset=0时，计数器置数操作。VHDL语言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu ISPORT(ud : IN STD_LOGIC;s : IN STD_LOGIC;reset : IN STD_LOGIC;d3,d2,d1,d0 : IN std_logic;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jishu;ARCHITECTURE jishu_architecture OF jishu ISBEGIN process(ud,s,reset,clk) begin if(reset='0') then q(3)<=d3; q(2)<=d2; q(1)<=d1; q(0)<=d0; else if(s='1') then q<=q; else if(clk'event and clk='1') then if(ud='1') then if(q="0000") then q<="1001" else q<=q-1; end if; else if(q="1001") then q<="0000" else q<=q+1; end if; end if; else q<=q; end if; end if; end if; end process;END jishu_architecture;4、译码模块通过加减计数得到译码器输出。加减计数、译码显示真值表：时钟加/减控制计数器输出译码器输出clkUd 0000000011111110 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0 1 0 0 00 0 0 1 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1译码图形：VHDL语言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY yima ISPORT(a : IN STD_LOGIC_VECTOR(3 downto 0);y : OUT STD_LOGIC_VECTOR(9 downto 0);END yima;ARCHITECTURE yima_architecture OF yima ISBEGIN process(a) begin case a is when "0000" => y<="0000000001" when "0001" => y<="0000000010" when "0010" => y<="0000000100" when "0011" => y<="0000001000" when "0100" => y<="0000010000" when "0101" => y<="0000100000" when "0110" => y<="0001000000" when "0111" => y<="0010000000" when "1000" => y<="0100000000" when others => y<="1000000000" end case; end process; END yima_architecture;5、控制模块1、设置甲乙两方击球脉冲信号in1、in2，甲方击球信号使得加减计数器加法计数，乙方击球信号使得加减计数器减法计数，译码模块输出端Y1-Y8接LED模拟乒乓球的轨迹，Y0、Y9为球掉出桌外信号，控制模块实现移位方向的控制。2、设置发球权拥有显示信号S1、S2，控制模块使每两次交换发球权。3、设置捡球信号reset1，通过加减计数模块的异步置数端实现捡球，当甲方拥有发球权时，捡球信号将球放到Y1；乙方拥有发球权时，捡球信号将球放到Y8。4、对甲、乙双方的得分进行检测，只要有一方的得分达到11，则一局结束。5、设置裁判复位信号reset，在每局结束后将双方得分清零。控制模块与译码模块和加减计数模块的连接：部分控制模块中VHDL语言及图形：1、jishu2LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu2 ISPORT(clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(1 downto 0);END jishu2;ARCHITECTURE jishu2_architecture OF jishu2 ISBEGIN process(clk) begin if(clk'event and clk='1') then if(q="11") then q<="00" else q<=q+1; end if; end if; end process;END jishu2_architecture;2、xuanzeLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY xuanze ISPORT(a : IN STD_LOGIC;q1: in std_logic;q2: in std_logic;q : out STD_LOGIC);END xuanze;ARCHITECTURE xuanze_architecture OF xuanze ISBEGIN process(a) begin if(a='1') then q<=q2; else q<=q1; end if; end process;END xuanze_architecture;3、dchufaqiLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY dchufaqi ISPORT(d : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC);END dchufaqi;ARCHITECTURE dchufaqi_architecture OF dchufaqi ISBEGIN process(clk) begin if(clk'event and clk='0') then q<=d; else q<=q; end if; end process;END dchufaqi_architecture;6、核心问题1、由于实验箱上的频率为50MHz，译码器输出变化太快，显示在实验箱上的8个LED闪亮变化太快，以致无法识别。因此需要降低频率后在接到加减计数模块的clk端。图形：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yanshi is port (clk: in std_logic;y: buffer std_logic_vector(24 downto 0) );end yanshi;architecture behave of yanshi isVHDL语言： begin process(clk) begin if(clk'event and clk='1') then if(y="1000000000000000000000000" or y="1111111111111111111111111") then y<="0000000000000000000000000" else y<=y+1; end if; end if; end process;end behave;2、在数码管上动态显示甲乙双方的得分。动态显示模块：1、dongtaixianshi1的VHDL语言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi1 is port ( clk: IN STD_LOGIC;y: buffer std_logic_vector(1 downto 0) );end dongtaixianshi1; architecture behave of dongtaixianshi1 is begin process(clk) begin if(clk'event and clk='1') then if(y="11") then y<="00" else y<=y+1; end if; end if; end process;end behave;2、dongtaixianshi2的VHDL语言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi2 is port (a: in std_logic_vector(1 downto 0);yjia1,yjia0,yyi1,yyi0: in STD_LOGIC_VECTOR(6 downto 0);y: out std_logic_vector(6 downto 0);pianxuan: out std_logic_vector(3 downto 0) );end dongtaixianshi2; architecture behave of dongtaixianshi2 is begin process(a) begin case a is when "00" => y<=yjia1;pianxuan<="0111" when "01" => y<=yjia0;pianxuan<="1011" when "10" => y<=yyi1;pianxuan<="1101" when OTHERS => y<=yyi0;pianxuan<="1110" end case; end process;end behave;三、结果分析注：本实验采取实际测试的方法。采用Altera新一代的MAX器件EPM570T100C5。 程序下载方法采用ByteBlaster。1、分配引脚：符号分配引脚名称备注in1pin_27K201选手甲，按下即为击球。in2pin_30K204选手乙，按下即为击球。resetpin_33S205裁判，拨盘开关拨到左边即为将双方得分清零。clkpin_62CLK时钟信号。reset1pin_34S206裁判，拨盘开关先拨到左边后拨到右边即为分配发球权。y18pin_50D208Y18.1连到实验箱的8个LED。当Y18亮时，要求乙迅速击球，当Y11亮，要求甲迅速击球。若击中，点亮的LED会依次从左到右或从右到左；若未击中，球跳出桌外，对方得一分。y17pin_49D207y16pin_48D206y15pin_47D205y14pin_42D204y13pin_41D203y12pin_40D202y11pin_38D201y6pin_81a显示计分y5pin_82by4pin_83cy3pin_84dy2pin_85ey1pin_86fy0pin_87gpianxuan3pin_91S0pianxuan2pin_92S1pianxuan1pin_99S6pianxuan0pin_100S72、分析：（1）经测试，完全符合要求。（2）上述设计的乒乓球比赛游戏机用到了自下而上的层次化设计方法，用到了VHDL语言设计输入方法和原理图设计输入方法。（3）由调节晶振产生的时钟脉冲信号的频率，可以调节球的运动速度。四、附件1、完整电路图2、各个自制元件的VHDL程序（1）dchufaqiLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY dchufaqi ISPORT(d : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC);END dchufaqi;ARCHITECTURE dchufaqi_architecture OF dchufaqi ISBEGIN process(clk) begin if(clk'event and clk='0') then q<=d; else q<=q; end if; end process;END dchufaqi_architecture;（2）dongtaixianshi1library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi1 is port ( clk: IN STD_LOGIC;y: buffer std_logic_vector(1 downto 0) );end dongtaixianshi1; architecture behave of dongtaixianshi1 is begin process(clk) begin if(clk'event and clk='1') then if(y="11") then y<="00" else y<=y+1; end if; end if; end process;end behave;（3）dongtaixianshi2library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi2 is port (a: in std_logic_vector(1 downto 0);yjia1,yjia0,yyi1,yyi0: in STD_LOGIC_VECTOR(6 downto 0);y: out std_logic_vector(6 downto 0);pianxuan: out std_logic_vector(3 downto 0) );end dongtaixianshi2; architecture behave of dongtaixianshi2 is begin process(a) begin case a is when "00" => y<=yjia1;pianxuan<="0111" when "01" => y<=yjia0;pianxuan<="1011" when "10" => y<=yyi1;pianxuan<="1101" when OTHERS => y<=yyi0;pianxuan<="1110" end case; end process;end behave;（4）fenpinlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin is port ( clk: in std_logic; clk1: out std_logic );end fenpin; architecture behave of fenpin issignal cnt1: std_logic_vector(25 downto 0);begin process(clk) begin if(clk'event and clk='1') then cnt1<=cnt1+1; end if; end process; clk1<=cnt1(15);end behave;（5）jifenLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jifen ISPORT(reset : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jifen;ARCHITECTURE jifen_architecture OF jifen ISBEGIN process(clk,reset) begin if(reset='0') then q<="0000" elsif(clk'event and clk='1') then if(q="1011") then q<="1011" else q<=q+1; end if; end if; end process;END jifen_architecture;（6）jishuLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu ISPORT(ud : IN STD_LOGIC;s : IN STD_LOGIC;reset : IN STD_LOGIC;d3,d2,d1,d0 : IN std_logic;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jishu;ARCHITECTURE jishu_architecture OF jishu ISBEGIN process(ud,s,reset,clk) begin if(reset='0') then q(3)<=d3; q(2)<=d2; q(1)<=d1; q(0)<=d0; else if(s='1') then q<=q; else if(clk'event and clk='1') then if(ud='1') then if(q="0000") then q<="1001" else q<=q-1; end if; else if(q="1001") then q<="0000" else q<=q+1; end if; end if; else q<=q; end if; end if; end if; end process;END jishu_architecture;（7）jishu2LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu2 ISPORT(clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(1 downto 0);END jishu2;ARCHITECTURE jishu2_architecture OF jishu2 ISBEGIN process(clk) begin if(clk'event and clk='1') then