二输入与非门、或非门版图设计.pdf

.课程名称Course与非门电路的版图：集成电路设计技术项目名称Item二输入与非门、或非门版图设计.spc 文件（瞬时分析） ：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:03.include H:ml2_125.mdVPower VDD GND 5va A GND PULSE (0 5 0 5n 5n 100n 200n).vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B) v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * * * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6.5)* 4 = F (42.5,6.5)* 6 = GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u* M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u* M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M3 F B 5 GND NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u* M3 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5)M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u* M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END与非门电路仿真波形图（瞬时分析） ：.spc 文件（直流分析） ：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:03.include H:ml2_125.mdVPower VDD GND 5va A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * .* * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6.5)* 4 = F (42.5,6.5)* 6 = GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u* M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u* M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M3 F B 5 GND NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u* M3 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5)M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u* M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END与非门电路仿真波形图（直流分析） ：或非门电路的版图：.spc 文件（瞬时分析） ：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va A GND PULSE (0 5 0 5n 5n 100n 200n)vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B) v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * .* * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * * * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6)* 4 = F (42.5,6.5)* 5 = GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u* M1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u* M2 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M3 F A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=104.5p PS=60u* M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)M4 GND B F GND NMOS L=2u W=9.5u AD=104.5p PD=60u AS=57p PS=31u* M4 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END或非门电路仿真波形图（瞬时分析） ：.spc 文件（直流分析） ：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * .* * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6)* 4 = F (42.5,6.5)* 5 = GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u* M1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u* M2 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M3 F A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=104.5p PS=60u* M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)M4 GND B F GND NMOS L=2u W=9.5u AD=104.5p PD=60u AS=57p PS=31u* M4 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END或非门电路仿真波形图（直流分析） ：.课程名称Course集成电路设计技术项目名称Item二输入与非门、或非门版图设计目的1. 掌握利用 E-EDIT 进行 IC 设计方法，设计二输入与非门版图并仿真Objective2. 掌握利用 L-EDIT 进行 IC 设计方法，设计二输入或非门版图并仿真3. 领会并掌握版图设计最优化实现方法。.内容（方法、步骤、要求或考核标准及所需工具、设备等）一、实训设备与工具1 PVI 计算机一台；2 Tanner Pro 集成电路设计软件二、实训方法、步骤与要求1 二输入与非门电路的线路结构2 二输入或非门电路的线路结构3 CMOS 倒相器电路的版图.4 根据与非门、或非门线路结构，在一个工程中，重新新建两个新 CELL，分别对应与非门和或非门版图，并设计与非门、或非版图结构。1） 按照最佳噪声容限合理设计与非门、或非门单元电路中的N 管和 P 管的尺寸；2） 版图结构最简单，版图尺寸最小； （高度均为 70um）3） 加入正确的电路端口，并在抽取的网表中存在A、B 和 F；4） 版图设计规则检查（DRC）无错误5 熟记基本、重要的版图设计规则6 进行 CMOS 与非门、或非门版图网表抽取，加入仿真命令，进行瞬时和直流分析 Tool Extract General 选项 Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext Spice Extract Output File: d:designnand2.spc Output 选项 Comment: Write Node name Names Write Verbose Spice Statement Spice Include Statement . Include c:tannermodelsml2_125.md插入相应的仿真命令，则可进行二输入与非门、或非门的瞬时或直流仿真7合理设计三输入与或非门、或与非门的N 管和 P 管尺寸与版图结构。8合理设计三输入与或非门、或与非门的N 管和 P 管尺寸与版图结构。三、注意事项：1）如果对版图设计的基本规则不熟悉，可以在L-EDIT 中，打开 SETUP DRC，列出了所有的设计规则，可学习和记忆其中的一些主要和常用的版图设计规则2）在进行版图设计规则检查时，应选择输出检查文件一项，版图设计中出现的所有错误，都可以在该输出文件中列出，并标明出错的原因，与哪条规则相违背，可打开规则进行对照，并在版图上进行相应的修改。.