根据VHDL的空调控制器设计.doc

.-数字系统设计与硬件描述语言期末考试作业题目： 空调控制器的设计 学院： 电子信息工程学院 专业： 物联网工程 学号： 3014204328 姓名： 刘涵凯 2016-12-14一、 选题设计描述1. 功能介绍设计内容为空调控制器，可实现空调的开关、模式切换、温度控制、风速控制、定时设置。模式默认为制冷，可切换为制热、除湿。温度默认为26度，可按“温度+”、“温度-”调节，每次调节1度，最高30度，最低16度。风速默认为中挡，可按“风速+”、“风速-”切换为低挡、高挡、睡眠模式。睡眠模式中，在低挡与停止间循环。定时设置默认关闭，开启时默认30分钟，可按“定时+”、“定时-”调节，每次调节30分钟，最高24小时，最低30分钟。定时倒计时结束时，关闭空调。定时开启时，可按“取消定时”关闭定时。空调控制器模拟界面如下：2. 算法简介1）空调控制器 其输入与输出在主程序kt中已标明，在此不做介绍。2）单脉冲模块这是非常重要以及核心的模块。当a产生一个上升沿时，输出一个单脉冲，脉冲将持续到经过一个clk上升沿后的clk下降沿。3）开关模块a连接空调的开关，b连接开关控制模块的输出，c为空调各工作模块的开关信号，d连接数码管显示开关状况。当定时时间结束，b输入一个单脉冲，空调关闭。4）开关控制模块此模块的作用是保证开关模块能够正常工作。开关打开时，a输入一个单脉冲，重置c。b连接定时模块，当定时结束，b输入一个单脉冲，使c输出1，使开关模块输出05）温度模块a连接开关模块，b为温度+1，c为温度-1，输出为温度的十位和个位。6）风速模块a连接开关模块，b为风速+1，c为风速-1。di，zhong，gao为抵挡、中挡、高挡的状态（无睡眠模式，因为睡眠模式是抵挡-停止模式）。其他连接数码管，显示睡眠模式、抵挡、中挡、高挡的状态。7）模式模块b连接开关模块，c为切换模式，输出类似于模式模块。8）定时模块a连接开关模块，b为定时模块开启，c为取消定时，up、down为定时时间+、-。clk1为空调时钟，clk2为模拟的倒计时时钟（周期1分钟）。clk2周期远大于clk1。当时间倒计时结束时，sw1输出1，使开关控制模块控制开关关闭。其他输出连接倒计时模块。9）倒计时模块a连接开关模块，clk连接定时模块的clk2，输入时间发生变化时，重新倒计时。倒计时结束时，finish输出1，使定时模块的sw1输出1。10）数码管模块a连接开关模块，此为7段译码器。11）计数器模块此为六位计数器。a连接睡眠模式开关，rst为睡眠模式打开时的重置信号，每6次输出一次1。二、 程序源代码及说明1）空调控制器LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY kt IS PORT(switchin,modeset,fanup,fandown,tempup,tempdown,timerop,timercancel,timerup,timerdown,clk1,clk2: IN STD_LOGIC; -电源开关、模式切换、风速+、风速-、温度+、温度-、定时、取消定时、定时+、定时-、时钟信号、倒计时时钟信号 cools,heats,drys,dis,zhongs,gaos: OUT STD_LOGIC; -通向空调内部的制冷、制热、除湿、抵挡、中挡、高挡状态输出 switchstate,tempd,temps,coolstate,heatstate,drystate,distate,zhongstate,gaostate,sleepstate,hdstate,hsstate,tdstate,tsstate: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -由数码管显示的开关、温度、制冷、制热、除湿、抵挡、中挡、高挡、睡眠状态和倒计时剩余时间END ENTITY kt;ARCHITECTURE behave OF kt ISCOMPONENT switch -开关模块 PORT(a,b,clk: IN STD_LOGIC; -b受定时模块的控制，时间减为0时，关闭开关 c: OUT STD_LOGIC; d: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -输送给数码管 END COMPONENT switch; COMPONENT control -开关控制模块 PORT(a,b,clk: IN STD_LOGIC; c: OUT STD_LOGIC); END COMPONENT control; COMPONENT fan -风速模块 PORT(a,b,c,clk: IN STD_LOGIC; di,zhong,gao: OUT STD_LOGIC; -由于high和low是敏感词汇，所以此处用拼音，可以看到此处没有睡眠模式，是因为睡眠模式其实是抵挡-停止模式 ssleep,sdi,szhong,sgao: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -不同于发给空调内部的信号，睡眠模式的状态应显示在外 END COMPONENT fan; COMPONENT BCD7 -数码管模块 PORT(a: IN STD_LOGIC; b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(0 TO 6) ); END COMPONENT BCD7; COMPONENT pulse -单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; COMPONENT temp -温度模块 PORT(a,b,c,clk: IN STD_LOGIC; -a控制开关，b提高1度，c降低1度 temp1,temp2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT temp; COMPONENT timer -定时模块 PORT(a,b,c,up,down,clk1,clk2: IN STD_LOGIC; sw1: OUT STD_LOGIC; -总开关关闭信号 oh1,oh2,ot1,ot2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -输送给数码管显示剩余时间 END COMPONENT timer; COMPONENT mode PORT(b,c,clk: IN STD_LOGIC; cool,heat,dry: OUT STD_LOGIC; cool1,heat1,dry1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT mode;SIGNAL swa,swb,swc:STD_LOGIC;SIGNAL sigBCD7_1,sigBCD7_2,sigBCD7_3,sigBCD7_4,sigBCD7_5,sigBCD7_6,sigBCD7_7,sigBCD7_8,sigBCD7_9,sigBCD7_10,sigBCD7_11,sigBCD7_12,sigBCD7_13,sigBCD7_14:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINU1: switch PORT MAP(a=>switchin,b=>swb,c=>swa,clk=>clk1,d=>sigBCD7_1); U2: control PORT MAP(a=>switchin,b=>swc,clk=>clk1,c=>swb);U3: fan PORT MAP(a=>swa,b=>fanup,c=>fandown,clk=>clk1,di=>dis,zhong=>zhongs,gao=>gaos,ssleep=>sigBCD7_2,sdi=>sigBCD7_3,szhong=>sigBCD7_4,sgao=>sigBCD7_5); U4: temp PORT MAP(a=>swa,b=>tempup,c=>tempdown,clk=>clk1,temp1=>sigBCD7_6,temp2=>sigBCD7_7); U5: timer PORT MAP(a=>swa,clk1=>clk1,clk2=>clk2,b=>timerop,c=>timercancel,up=>timerup,down=>timerdown,sw1=>swc,oh1=>sigBCD7_8,oh2=>sigBCD7_9,ot1=>sigBCD7_10,ot2=>sigBCD7_11); U6: mode PORT MAP(b=>swa,c=>modeset,clk=>clk1,cool=>cools,heat=>heats,dry=>drys,cool1=>sigBCD7_12,heat1=>sigBCD7_13,dry1=>sigBCD7_14); U7: BCD7 PORT MAP(a=>swa,b=>sigBCD7_1,q=>switchstate); U8: BCD7 PORT MAP(a=>swa,b=>sigBCD7_2,q=>sleepstate); U9: BCD7 PORT MAP(a=>swa,b=>sigBCD7_3,q=>distate); U10: BCD7 PORT MAP(a=>swa,b=>sigBCD7_4,q=>zhongstate); U11: BCD7 PORT MAP(a=>swa,b=>sigBCD7_5,q=>gaostate);U12: BCD7 PORT MAP(a=>swa,b=>sigBCD7_6,q=>tempd); U13: BCD7 PORT MAP(a=>swa,b=>sigBCD7_7,q=>temps); U14: BCD7 PORT MAP(a=>swa,b=>sigBCD7_8,q=>hdstate); U15: BCD7 PORT MAP(a=>swa,b=>sigBCD7_9,q=>hsstate); U16: BCD7 PORT MAP(a=>swa,b=>sigBCD7_10,q=>tdstate);U17: BCD7 PORT MAP(a=>swa,b=>sigBCD7_11,q=>tsstate); U18: BCD7 PORT MAP(a=>swa,b=>sigBCD7_12,q=>coolstate); U19: BCD7 PORT MAP(a=>swa,b=>sigBCD7_13,q=>heatstate); U20: BCD7 PORT MAP(a=>swa,b=>sigBCD7_14,q=>drystate); PROCESS(clk1)BEGINEND PROCESS;END ARCHITECTURE behave;2）单脉冲模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY pulse IS -单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC);END ENTITY pulse;ARCHITECTURE behave OF pulse ISSIGNAL d:STD_LOGIC:=0;SIGNAL f:STD_LOGIC:=0;SIGNAL g:STD_LOGIC:=0; -确保经过第一个clk上升沿时输出1SIGNAL h:STD_LOGIC:=0; -同上BEGINPROCESS(a,clk) BEGINIF(clkEVENT AND clk=1)THENIF(f=1)THENg<=1;ELSE g<=0;END IF;END IF;END PROCESS;PROCESS(a,clk) BEGINIF(clkEVENT AND clk=0)THENIF(a=1)THENIF(f=1)THENIF(g=1)THEN d<=1;ELSE d<=0;END IF;ELSE d<=1;END IF;ELSE d<=0; -a为0时，重置此单脉冲发生器END IF;END IF;END PROCESS;PROCESS(d) BEGINIF(a=1)THENIF(d=1)THENf<=0; ELSE f<=1;END IF;ELSE f<=0;END IF;b<=f;END PROCESS;END ARCHITECTURE behave;3）开关模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY switch IS -开关模块 PORT(a,b,clk: IN STD_LOGIC; -b受定时模块的控制，时间减为0时，关闭开关 c: OUT STD_LOGIC; d: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -输送给数码管END ENTITY switch;ARCHITECTURE behave OF switch ISCOMPONENT pulse -调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;BEGINU1: pulse PORT MAP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN IF(clkEVENT AND clk=1)THEN IF(p1=1)THEN -空调开关打开 c<=1;d<="0001" END IF; IF(p2=1)THEN -时间减为0时，定时模块返回1，关闭开关 c<=0;d<="0000" END IF; END IF; END PROCESS;END ARCHITECTURE behave;4）开关控制模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY control IS -开关控制模块 PORT(a,b,clk: IN STD_LOGIC; c: OUT STD_LOGIC);END ENTITY control;ARCHITECTURE behave OF control ISCOMPONENT pulse -调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;BEGINU1: pulse PORT MAP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN IF(clkEVENT AND clk=1)THEN IF(p1=1)THEN -空调开关打开 c<=0; END IF; IF(p2=1)THEN -时间减为0时，定时模块返回1，关闭开关 c<=1; END IF; END IF; END PROCESS;END ARCHITECTURE behave;5）温度模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY temp IS -温度模块,最高30度，最低16度，默认26度 PORT(a,b,c,clk: IN STD_LOGIC; -a控制开关，b提高1度，c降低1度 temp1,temp2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY temp;ARCHITECTURE behave OF temp ISCOMPONENT pulse -调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL t1 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL t2 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;SIGNAL p3 : STD_LOGIC:=0;BEGINU1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); U3: pulse PORT MAP(a=>a,b=>p3,clk=>clk); PROCESS(a,clk)BEGIN IF(clkEVENT AND clk=1)THEN IF(p3=1)THEN -开关打开时，默认26度 t1<="0010"t2<="0110"ELSIF(a=0)THEN t1<="0000"t2<="0000"END IF; IF(a=1)THENIF(p1=1)THEN -判断"温度+"按键按下IF(t1="0011")THEN t1<="0011"t2<="0000" ELSIF(t2="1001")THENt1<=t1+1; t2<="0000" ELSE t2<=t2+1; END IF; END IF; IF(p2=1)THEN -判断"温度-"按键按下 IF(t1="0001")THEN IF(t2="0110")THEN t1<="0001"t2<="0110"ELSE t2<=t2-1; END IF; ELSIF(t2="0000")THEN t1<=t1-1; t2<="1001" ELSE t2<=t2-1; END IF; END IF;ELSE t1<="0000"t2<="0000"END IF; END IF;temp1<=t1;temp2<=t2;END PROCESS;END ARCHITECTURE behave;6）风速模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY fan IS -风速模块：睡眠、低、中、高；默认中挡；睡眠模式在低挡和停止之间循环 PORT(a,b,c,clk: IN STD_LOGIC; di,zhong,gao: OUT STD_LOGIC; -由于high和low是敏感词汇，所以此处用拼音，可以看到此处没有睡眠模式，是因为睡眠模式其实是抵挡-停止模式 ssleep,sdi,szhong,sgao: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -不同于发给空调内部的信号，睡眠模式的状态应显示在外END ENTITY fan;ARCHITECTURE behave OF fan ISCOMPONENT pulse -调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; COMPONENT count6 -调用计数器 PORT ( a,clk,rst : IN STD_LOGIC; o: OUT STD_LOGIC); END COMPONENT count6; SIGNAL e : STD_LOGIC_VECTOR(2 DOWNTO 0):="000" -停止000、睡眠001、抵挡010、中挡011、高挡100SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;SIGNAL p3 : STD_LOGIC:=0;SIGNAL op : STD_LOGIC:=0;SIGNAL op1 : STD_LOGIC:=0; -其上升沿用于开启睡眠模式SIGNAL op2 : STD_LOGIC:=0; SIGNAL rst1 : STD_LOGIC:=0;SIGNAL rst2 : STD_LOGIC:=0;SIGNAL change : STD_LOGIC:=0;SIGNAL m : STD_LOGIC:=0; -睡眠模式中使用，由于睡眠模式是循环模式，所以不设置置0BEGIN -模式在按键操作下可循环滚动U1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); U3: pulse PORT MAP(a=>a,b=>p3,clk=>clk); U4: pulse PORT MAP(a=>rst1,b=>rst2,clk=>clk); U5: count6 PORT MAP(a=>op,rst=>rst2,clk=>clk,o=>change); PROCESS(a,clk)BEGIN IF(clkEVENT AND clk=1)THEN op1<=op2;IF(p3=1)THEN -开关打开时，默认中挡 e<="011"ELSIF(a=0)THEN e<="000"END IF; IF(a=1)THENIF(p1=1)THEN -判断"风速+"按键按下IF(e="100")THEN -高挡时按下，则切换为睡眠 e<="001"op1<=1; ELSE e<=e+1;op1<=0; END IF; END IF; IF(p2=1)THEN -判断"风速"-"按键按下 IF(e="001")THEN -睡眠时按下，则切换为高挡 e<="100"op1<=0;ELSIF(e="010")THENe<=e-1;op1<=1;ELSE e<=e-1;op1<=0; END IF; END IF;ELSE e<="000"END IF; END IF;END PROCESS;PROCESS(change)BEGINIF(changeEVENT AND change=1)THENIF(m=1)THENm<=0;ELSE m<=1;END IF;END IF;END PROCESS; PROCESS(e)BEGINop2<=op1;IF(e="001")THEN -睡眠时的低挡-停止循环IF(op2EVENT AND op2=1)THENop<=1;rst1<=1;END IF;op<=1;CASE m IS WHEN 1 => di<=1;zhong<=0;gao<=0;ssleep<="0001"sdi<="0000"szhong<="0000"sgao<="0000" WHEN 0 => di<=0;zhong<=0;gao<=0;ssleep<="0001"sdi<="0000"szhong<="0000"sgao<="0000" END CASE;ELSEop<=0;-关闭睡眠模式 IF(e="010")THEN di<=1;zhong<=0;gao<=0;ssleep<="0000"sdi<="0001"szhong<="0000"sgao<="0000" ELSIF(e="011")THEN di<=0;zhong<=1;gao<=0;ssleep<="0000"sdi<="0000"szhong<="0001"sgao<="0000" ELSIF(e="100")THEN di<=0;zhong<=0;gao<=1;ssleep<="0000"sdi<="0000"szhong<="0000"sgao<="0001" ELSIF(e="000")THEN di<=0;zhong<=0;gao<=0;ssleep<="0000"sdi<="0000"szhong<="0000"sgao<="0000" END IF; END IF; END PROCESS;END ARCHITECTURE behave;7）模式模块LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY mode IS -模式模块：制冷、制热、除湿 PORT(b,c,clk: IN STD_LOGIC; cool,heat,dry: OUT STD_LOGIC; cool1,heat1,dry1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY mode;ARCHITECTURE behave OF mode ISCOMPONENT pulse -单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL e : STD_LOGIC_VECTOR(1 DOWNTO 0):="00"SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;BEGINU1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); PROCESS(b,c,p1,p2,clk) -按键选择模式BEGINIF(clkEVENT AND clk=1)THENIF(b=1)THENIF(p1=1)THEN -默认制冷模式e<="01"END IF;IF(p2=1)THENIF(e="11")THENe<="01"ELSE e<=e+1;END IF;END IF;ELSE e<="00"END IF;END IF;END PROCESS; PROCESS(e)BEGIN -由于第一个PROCESS中，a为0时e为"00"，所以此处不再考虑a CASE e IS WHEN "01" => cool<=1;heat<=0;dry<=0;cool1<="0001"heat1<="0000"dry1<="0000" WHEN "10" => cool<=0;heat<=1;dry<=0;cool1<="0000"heat1<="0001"dry1<="0000"WHEN "11" => cool<=0;heat<=0;dry<=1;cool1<="0000"heat1<="0000"dry1<="0001"WHEN OTHERS => cool<=0;heat<=0;dry<=0;cool1<="0000"heat1<="0000"dry1<="0000" END CASE; END PROCESS;END ARCHITECTURE behave;8）定时模块ENTITY timer IS -定时模块：最低30分钟，最高24小时，每次按键调整30分钟，可取消定时 PORT(a,b,c,up,down,clk1,clk2: IN STD_LOGIC; sw1: OUT STD_LOGIC; -总开关关闭信号 oh1,oh2,ot1,ot2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -输送给数码管显示剩余时间END ENTITY timer;ARCHITECTURE behave OF timer ISCOMPONENT pulse -调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; COMPONENT cd -调用倒计时模块 PORT(a,clk: IN STD_LOGIC; time1,time2,time3,time4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); finish: OUT STD_LOGIC; outtime1,outtime2,outtime3,outtime4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT cd; SIGNAL cl : STD_LOGIC:=0; SIGNAL op : STD_LOGIC:=0;SIGNAL p1 : STD_LOGIC:=0;SIGNAL p2 : STD_LOGIC:=0;SIGNAL p3 : STD_LOGIC:=0;SIGNAL sw : STD_LOGIC:=0;-倒计时模块开关信号SIGNAL h11 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL h22 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL t11 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0011"SIGNAL t22 : STD_LOGIC_VECTOR(3 DOWNTO 0)