2022年AN_编程手册[归 .pdf

Rev. 0.61 5/08Copyright ? 2008 by Silicon LaboratoriesAN230AN230Si4700/01/02/03 PROGRAMMING GUIDE1. Introduction1.1. ScopeThis document applies to Si4700/01/02/03 firmware revision 15 and greater and example code version 2 andgreater. Refer to for example code.1.2. PurposeThe purpose of this programming guide is to describe the following:Device initialization sequence and busmode selection2-wire and 3-wire busmodesStep-by-step procedures for setting default configurationchannel selectionseek up/seek downRDS/RBDSThis document references the Si4700/01 and Si4702/03 data sheets.1.3. TerminologySENB or SENserial enable pin, active low, used only for 3-wire operationSDIOserial data in/data out pin.SCLK serial clock pin.RSTB or RSTreset pin, active lowDevice refers to the Si4700/01/02/03名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 42 页 - - - - - - - - - AN2302Rev. 0.61名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 2 页，共 42 页 - - - - - - - - - AN230Rev. 0.613TABLEOF CONTENTS1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.2. Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12. Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42.1. Power, Initialization Sequence, and Busmode Selection . . . . . . . . . . . . . . . . . . . . . .42.2. 3-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.3. 2-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93. Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2. Hardware Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.3. General Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4. Regional Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183.5. End User Adjustable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.6. Seek Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.7. Tune Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223.8. RDS/RBDS (Si4701/03 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244. Programming with Commands (Si4702/03 Rev C or later device ONLY) . . . . . . . . . . .264.1. Programming in Command in 2-wire Control Interface Mode . . . . . . . . . . . . . . . . . .274.2. Programming in Command in 3-write Control Interface Mode . . . . . . . . . . . . . . . . .285. Command and Properties (Si4702/03 Rev C and later device ONLY) . . . . . . . . . . . . . .305.1. Si4702/03 Commands (Si4702/03 Rev C or later device ONLY) . . . . . . . . . . . . . . .315.2. Si4702/03 Properties (Si4702/03 Rev C or later device ONLY) . . . . . . . . . . . . . . . .33Appendix Seek Adjustability and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Default Seek Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Advanced Seek Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Seek Algorithm Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Seek Results Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Seek Settings Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Revision 0.42 to Revision 0.43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Revision 0.43 to Revision 0.44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Revision 0.44 to Revision 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Revision 0.5 to Revision 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Revision 0.6 to Revision 0.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 3 页，共 42 页 - - - - - - - - - AN2304Rev. 0.612. Hardware Description2.1. Power, Initialization Sequence, and Busmode SelectionFigure1. Initialization SequenceVA,VD SupplyRCLK PinENABLE Bit12345RST PinVIO Supply名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 4 页，共 42 页 - - - - - - - - - AN230Rev. 0.6152.1.1. Hardware InitializationThe FM tuner device is capable of communicating using either a 3-wire or 2-wire interface. The selection of thisinterface is made during the reset sequence.Figure 1 demonstrates the sequencing of hardware events relative to reset. Figure2 combines this informationwith the setting of the ENABLE and DISABLE bits to better describe the possible combinations. The following stepsshould be used to initialize the device properly.1.Supply VA and VD.2.Supply VIO while keeping the RST pin low. Note that power supplies may be sequenced in any order (steps 1 and 2 may be reversed).3.Configure the proper pins for bus mode selection. See Figure3, “Powerup, Powerdown, and Reset Flowchart,” on page 7.4.Set the RST pin high. The device registers may now be read and written.5.Provide RCLK. If using the internal oscillator option, the XOSCEN bit must be set 500ms prior to setting the ENABLE bit to ensure that the oscillator has stabilized. A similar delay may be necessary for some external oscillator circuits. Please determine the necessary stabilization time for the clock source in the system.6.Si4703-C19 Errata Solution 2: Set RDSD = 0 x0000. Note that this is a writable register.7.Set the ENABLE bit high and the DISABLE bit low to powerup the device.Unpredictable behavior could result if a non-zero value is present in the RDSD register of the Si4703-C19 when it is enabled. Note that no other device will experience this behavior. There are three solutions available to ensure a zero value in the RDSD register when the Si4703-C19 is enabled and only one solution need be selected.a. Solution 1Generate a hard reset before enabling the tuner to clear the RDSD register. This is described in steps 2, 3, and 4 above and in step 1, To power up the device (after power down), of 2.1.2. Hardware Powerdown ” below. This must be done every time the tuner is enabled.b. Solution 2Write a zero value to the RDSD register before enabling the tuner. This is described in step 6 above and must be done every time the tuner is enabled.c. Solution 3Disable RDS by setting RDS = 0 before disabling the tuner. This is described in step 1, To power down the device, of 2.1.2. Hardware Powerdown” below and must be done every time the tuner is disabled. When the device is disabled, the RDSD register is automatically set to zero in preparation for the next time the device is enabled.2.1.2. Hardware PowerdownA powerdown mode is available to reduce power consumption when the part is idle. Setting both the ENABLE bithigh and the DISABLE bit high starts the powerdown sequence. This disables analog and digital circuitry whilemaintaining register configuration and keeping the bus active. Note that the device automatically sets the ENABLEbit low after the internal powerdown sequence completes. Setting the ENABLE bit low directly will cause the deviceto partially powerdown and should be avoided. See Figure2. Setting the ENABLE bit high and the DISABLE bit lowwill bring the device out of powerdown mode and resume normal operation. Refer to Figure1 for more information.To power down the device:1.Si4703-C19 Errata Option 3: Set RDS = 0.2.Set the ENABLE bit high and the DISABLE bit high to place the device in powerdown mode. Note that all register states are maintained so long as VIO is supplied and the RST pin is high.3.Remove VA and VD supplies as needed.To power up the device (after power down):1.Si4703-C19 Errata Option 1: Perform a hard reset of the tuner by following steps 2, 3, and 4 of 2.1.1 Hardware Initialization.2.Note that VIO is still supplied in this scenario. If VIO is not supplied, refer to device initialization procedure above.名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 5 页，共 42 页 - - - - - - - - - AN2306Rev. 0.613.Supply VA and VD.4.Set the ENABLE bit high and the DISABLE bit low to powerup the device.Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, anddisable the bus. Setting the RST pin high will bring the device out of reset, place the device in powerdown mode,and latch which bus mode will be used to communicate with the device. There are two methods for selecting thebus mode. Method one uses the SEN and SDIO pins while method two uses GPIO1 and GPIO3 (See Figure3).Please refer to the data sheet for more information regarding bus selection and timing requirements of the RSTsignal.More details on the register access during powerup and powerdown can be found in Section 3.2.1.ENABLE(02h.0)/DISABLE (02h.6)Powerup Control on page 11.Figure2. Powerup, Powerdown, and Reset State DiagramLowpower,BusAccessibleNormalOperationUndesirable,DoNotUseLowpower,BusInactivePowerdownRead:ENABLE = 0DISABLE = 0InactiveRegisters reset to default valuesBus InactivePowerupRead:ENABLE = 1DISABLE = 0Partial PowerdownRead:ENABLE = 0DISABLE = XRST = VIOWrite :ENABLE = 1DISABLE = 0Write :ENABLE = 0DISABLE = XWrite :ENABLE = 1DISABLE = 0Write :ENABLE = 1DISABLE = 1RST = GNDVA OptionalVD OptionalVIO OptionalRCLK OptionalVIO must be supplied prior to the rising edge of resetVA OptionalVD OptionalVIO RequiredRCLK OptionalVA, VD, and RCLK must be supplied prior to writing ENABLE = 1VA RequiredVD RequiredVIO RequiredRCLK RequiredSi4703-C19 Errata: Ensure RDSD register is zero before enabling.VA OptionalVD OptionalVIO RequiredRCLK OptionalDevice StatusPower Supply Status名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 6 页，共 42 页 - - - - - - - - - AN230Rev. 0.617Figure3. Powerup, Powerdown, and Reset FlowchartInactiveGPIO3 = VIO?GPIO1 = VIO?YesControl Interface = 2-wire modeYesControl Interface = 3-wire modeNoSDIO = GND?SENb = GND?YesYesNoNoPowerdownControl Interface activatedRST = VIO?NoYesBusModeSelectMethod2Bus Mode Select Method 1Invalid OptionNoNote:See data sheet for further details.名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 7 页，共 42 页 - - - - - - - - - AN2308Rev. 0.612.2. 3-Wire Control InterfaceFor three-wire operation, a transfer begins when the SEN pin is set low on a rising SCLK edge. The control word islatched internally on rising SCLK edges and is nine bits in length, comprised of a four bit chip addressA7:A4 = 0110b, a read/write bit (read= 1 and write= 0), and a four bit register address, A3:A0. The ordering of thecontrol word is A7:A5, R/W, A4:A0, as shown in Figure4. For write operations, the serial control word is followed by a 16-bit data word and is latched internally on risingSCLK edges. The device does not latch the register write until the falling SCLK with SEN high.Refer to “3-Wire Control Interface Characteristics” and “3-Wire Control Interface Write Timing Parameters” of thedevice data sheet for more information.Figure4. 3-Wire Control Interface Write Timing DiagramFor read operations, a bus turn-around of half a cycle is followed by a 16-bit data word shifted out on rising SCLKedges. The transfer ends on the rising SCLK edge after SEN is set high. Note that 26 SCLK cycles are required fora transfer; however, SCLK may run continuously.Refer to “3-Wire Control Interface Characteristics” and “3-Wire Control Interface Read Timing Parameters” of thedevice data sheet for more information.Figure5. 3-Wire Control Interface Read Timing DiagramA3A2A1A0D15D14-D1D0A4WA5A6A7Address + W = 01100 xxxxData OutSCLKSDIOSEN26th clock required to latch the data.A3A2A1A0D15D14-D1D0A4RA5A6A7Address + R = 01110 xxxxData InSCLKSDIOSEN? Cycle Bus Turnaround26th clock required to latch the data.名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 8 页，共 42 页 - - - - - - - - - AN230Rev. 0.6192.3. 2-Wire Control InterfaceFor two-wire operation, a transfer begins with the START condition. A START condition is defined as a high to lowtransition on the SDIO pin while SCLK is high. Transitions for data bits must occur while the SCLK pin is low. Thebyte following the START is the control word. The control word is latched internally on rising SCLK edges and iseight bits in length, comprised of a seven bit device address equal to 0010000b and a read/write bit (read= 1 andwrite = 0). The ordering of the control word is A6:A0, R/W as shown below. The device remains in the read or writestate until the STOP condition is received. For write operations, the control word and device acknowledge is followed by an eight bit data word latchedinternally on rising edges of SCLK. The device always acknowledges the data by setting SDIO low on the nextfalling SCLK edge. Any number of data bytes may be written by repeating the write process without sending aSTOP condition. Device register addresses are incremented by an internal address counter, starting with the upperbyte of register 02h, followed by the lower byte of register 02h, and wrapping back to 00h at the end of the registerfile. The transfer is considered finished upon receipt of a STOP condition.Figure6. 2-Wire Control Interface Write Timing DiagramFor read operations, the control word and device acknowledge is followed by an eight bit data word shifted out onfalling SCLK edges. Any numbe