模拟前端架构比较数字接收机-外文翻译.docx

A COMPARISON OF ANALOG FRONT END ARCHITECTURESFOR DIGITAL RECEIVERSHolly Pekau Student Member, IEEE, University of Calgary TRLabs e-mail:pekauatips.caJames W. Haslett Fellow, IEEE, University of Calgary TRLabse-mail: haslettenel.ucalgary.caAbstractRadio receivers that perform analog to digital conversion closerto the antenna and do most of the signal processing in the digital domain are known as digital receivers. Digital receivers aredesirable because they can be more easilyre-congured for multista- dard operation, they can facilitate performance improvementsby using digital lters for signal processing, and they can potentia- lly realize savings in chip area, power consumption and cost. The denition of a digital receiver is general and there are several types of receiver architectures that fall into this category. Digitalreceiver architectures which have been proposed include direct RFNyquist sampling, RF bandpass sampling or sub-sampling, directIF Nyquist sampling, and IF bandpass sampling orsubsamp- ling.This paper compares these digital receiver architectures in various categories including susceptibility to aperture jitter and aperturedistortion, noise gure degradation due to aliasing, ease of anti-aliasing lter implementation, ease of ADC implemen- tation, linearity, power consumption, chip area, and re-congurability. System and circuit level simulations using a commercial RF simulator are performed to quantitatively compare the different digital receiver architectures in some of the aforementioned categories. Thefeasibility of using the proposed digital receiver architectures forvarious standards is then examined and a survey of published digital receiver architectures is presented.Keywords: Digital receiver, software radio, sub-sam1 IntroductionThe increasing demand for exible multi-standard, multi-bandradios increases and recent improvements in analog-to-digital converter technology have led to the development of software radios with digital receivers. In a software radio receiver, wideband analog-to-digital conversion that captures multiple channels of thesoftware radio node is performed closer to the antenna. In addition to the improved exibility of use with multiple standards overmultiple frequency bands, digital receivers offer potential savings in power consumption, circuit area, and cost, and can potentially realize performance improvements resulting from the use of digital lters. The denition of a digital or software receiver is general and encompasses numerous architectures with various types of analog front ends. These architectures include direct RF sampling,RF sub-sampling, IF sampling, and IF sub-sampling. The block diagram of an RF sampling or sub-sampling receiver is shown in. Figure 1: RF Sampling or sub-sampling receiver block diagramFigure 2: IF Sampling or sub-sampling receiver block diagramFig. 1 and the block diagram of an IF sampling or sub-samplingreceiver is shown in Fig. 2.In an RF or IF sampling receiver, sampling is done at at least twice the maximum RF or IF frequency, resulting in a sampled output at the RF or IF frequency. In an RF or IF sub-sampling receiver, sampling is done at at least twice the RF or IF bandwidth resulting is an aliased sampled output around multiples of the sampling frequency as shown in Fig. 3(a). There may be additional restrictions on the sampling frequency to avoid aliasing in the case of sub-sampling as described by Vaughan in 1.In this work we compare the different digital receiver architectures with respect to their susceptibility to aperture jitter and aperture distortion, noise gure degradation due to aliasing, ease of anti-aliasing lter implementation, ease of ADC implementation,linearity, power consumption, chip area, and re-congurability.Figure 3. Results of sub-sampling: (a) Aliasing of signal band to Nyquist band(b) Noise aliasing to Nyquist band (c) Noise aliasing when input is bandpass ltered prior to sub-sampling.2 Susceptibility to Clock Aperture JitterAperture jitter, or the sample-to-sample variation of the sampling instant relative to an ideal clock causes the signal-to-noise ratio (SNR) of an ideal sampling system given to be: (1)where fa is the input signal frequency being sampled and tjrms is the rms jitter. The above expression is an approximation based on the assumption that the input signal is sinusoidal and that the timing jitter has zero mean. A more generic form of the expression for the SNR in terms of the autocorrelations of the sampled signal and the timing jitter is given by Da Dalt in 2, but for this work, the approximate expression is more useful as it is a function of known parameters. The effective number of bits (ENOB) for an ADC is limited by the signal-to-noise-and-distortion ratio (SINAD) and is given by (2)Using the preceding expression and equation 1, the maximum achievable ADC resolution for an ideal ADC where SNR is limited only by aperture jitter can be plotted versus input frequency for several clock jitter values as shown in Fig. 4. Aperture jitter can cause additional performance degradation in sub-sampling systems 3. Jitter affects frequencies in the sampled signal spectrum that are aliased to the frequency band of interest but this effect can be mitigated by adequate anti-aliasing ltering. Additional jitter requirements in sub-sampling systems are imposed by the frequency being sampled and the signal bandwidth as discussed by Vaughan in 1. The jitter requirements imposed by the sub-sampling process become more stringent as the frequency being sampled increases but are independent of the jitter requirements imposed by the required ADC resolutionFigure 4: Number of ADC bits versus aperture jitterDespite the SNR degradation caused by clock jitter in both direct RF sampling and RF sub-sampling and the jitter requirements imposed by the sampling frequency limitations in RF sub-sampling, receivers using both types of RF sampling have been implemented for standards that do not require very high ADC resolution. Current state of the art commercial PLLs can achieve 0.25ps rms jitterat 800MHz. This low jitter would allow 12-bit analog-to-digital conversion to be done at 800MHz.3 Aperture DistortionAt the sampling instant, the transition of control signals from track to hold causes distortion in the sampled signal. The distortion can occur through a number of mechanisms that are dependent on the clock signal transition time, the signal characteristics,the sampling circuit architecture, the device geometries, and the fabrication technology. The distortion increases with input frequency, imposing stricter requirements on sampling switches and clock generation circuits as the frequency being sampled increases.The increase in distortion with frequency being sampled is difcult to quantify because it depends on multiple factors but several authors have quantied the total harmonic distortion caused by sample and hold settling time for specic sampling architectures 4 5. Required clock transition times are also dependent on the specic sampling architecture used, the maximum input frequency, and the required ADC resolution.4 Noise Figure Degradation due to Aliasing andEase of Anti-aliasing Filter ImplementationIn a sampling system, noise is folded from multiples of the sampling frequency to the Nyquist band, as shown in Fig 3(b). In order to reduce the noise folded to the Nyquist band from multiples of fs, the signal is usually bandpass ltered before sub-sampling as shown in Fig. 3(c). As the ratio of the sampling frequency to the maximum frequency being sampled is decreased, the potential amount of noise aliasing is increased, and the requirements of the anti-aliasing lter are increased. As the anti-aliasing lter requirements are increased, they become more difcult to design and to integrate on chip. The design of high quality on-chip lters at RF.Figure5. Sampled output spectrum of an RF sampling receiver (fRF = 2.42GHz, fs = 5GHz)frequencies is very difcult and is still an active area of research though advancements in Q-enhanced LC lters and in MEMs devices are making the realization of such lters more feasible.5 Ease of ADC ImplementationSpeed limitations in the design of ADCs make it difcult to perform analog to digital conversion at RF frequencies, especially at high resolutions. These speed limitations are due to the inherent speed limitations of the transistors used to design the ADCs and to the increase in power and area that is needed to achieve high resolution at high frequencies. Therefore, in the case of an RF sampling receiver where A/D conversion with sufcient resolution cannot be done at the RF frequency, discrete time ltering and decimation is done prior to A/D conversion as described in 6.6 LinearityIn addition to the usual second and third order intermodulation products that cause distortion in receivers, RF and IF sampling receivers are sensitive to distortion due to aliasing. Aliasing causes distortion products in the sampler input spectrum to appear in the Nyquist spectrum and is especially difcult to mitigate in the case of sub-sampling where the number of frequencies that alias to the Nyquist band is drastically increased. Figures 5 and 6 show the output spectra of an RF sampling and an RF sub-sampling receiver. The increased number of tones due to aliasing in the spectrum of the RF sub-sampling receiver is evident. Due to the effects of aliasing, sub-sampling receivers generally have poorer linearity and more stringent anti-aliasing lter requirements than Nyquist sampling receivers but this degradation in linearity may be difcult to capture using gures of merit such as third order intercept (IP3), which are geared to receiver front ends which do not perform sampling.RF sampling and sub-sampling receivers may suffer from distortion problems because all the gain is realized at the RF frequency and high gain with good linearity is generally more difcult to achieve at high frequency due to the increased effect of parasitics.Figure 6. Sampled output spectrum of an RF sub-sampling receiver (fRF = 2.42GHz, fs = 100M Hz)and the lower intrinsic gain of transistors at high frequencies. IF sampling and sub-sampling receivers may have degraded distortion performance compared to RF sampling receivers due to the use of a mixer which may introduce additional distortion products.7 Power Consumption, Circuit Complexity, Chip Area and RecongurabilityThe analog receiver front end power consumption, circuit complexity and chip area of an RF sampling receiver are generally less than those of an IF sampling receiver because fewer circuit blocks are used. However, different lter implementations at RF and IF frequencies may require very different amounts of chip area and consume different amounts of current so the comparison depends strongly on the design of the circuit blocks comprising the receiver. The power consumption of a complete RF sampling receiver including the digital base band may be higher than that of an IF sampling receiver due to the high power consumption of very high frequency digital signal processing. This problem may be mitigated by discrete time ltering and decimating the sampled RF signal before A/D conversion but this adds circuit complexity.RF sampling receivers are generally more re-congurable for multi-standard use than IF sampling receivers because they contain a smaller number of analog circuit blocks which are typically less congurable than digital circuits.8 Simulation ResultsTwelve sampling receiver architectures with an RF frequency of 2.42GHz were simulated using a commercial RF simulator. Three direct RF sampling and three RF sub-sampling architectures as shown in Fig. 1 were designed with different anti-aliasing lters with S21 responses shown in Fig. 7 and a sampling frequency of 5GHz for the direct sampling architectures and 100MHz for the sub-sampling architectures. Three direct IF sampling and three IF sub-sampling architectures were also designed with different antialiasing lters with S21 responses shown in Fig. 8, an IF frequency.Figure 7: S21 of RF bandpass lters used in RF and IF sampling receiversFigure 8: S21 of IF anti-aliasing lters used in IF sampling receiversof 100MHz, and sampling frequencies of 240MHz for the direct sampling architectures and 80MHz for the sub-sampling architectures. The architecture of the IF sampling and sub-sampling receivers is shown in Fig. 2, but the RF bandpass lters used for the three RF sampling receivers were left in place to further reduce noise aliasing and distortion. The same LNA with 28 dB of gain and the same sampler with 10dB of gain are used for all architectures. The same mixer with 0dB of gain is used for all the IF sampling and sub-sampling architectures. All lters were implemented as ideal lumped element LC topologies. Simulation results for the receivers are given in Table I. It can be seen that the noise performance of the sub-sampling architectures is consistently worse than that of the direct sampling architectures due to the effects of noise aliasing. The IF sampling architectures have lower noise gures than the RF sampling architectures despite the use of a noisy mixer, probably because two anti-aliasing lters are used in the IF sampling architectures. The linearity and power consumption of the RF sampling architectures are better because a mixer is not used. The output SNR and equivalent maximum A/D converter resolution in bits including the effects of a 1ps aperture jitter are calculated using the simulated noise gure and equation 1. It can be seen that aperture jitter dominates the noise performance of the RF sampling and RF sub-sampling receivers.9 Survey of Published RF and IF Sampling ReceiversTable II shows the sampled (RF or IF) and sampling frequencies of recent published RF and IF sampling receivers for various standards. It can be seen that IF sampling and sub-sampling receivers have been used for some of the more stringent radio standards such as GSM/EDGE and WCDMA whereas RF sampling and sub-sampling architectures have been limited to applications such as Bluetooth, radar, GPS, and certain WLAN applications with less stringent standards.TABLE ISIMULATED PERFORMANCE OF RF AND IF SAMPLING AND SUB-SAMPLING RECEIVERS (fs = SAMPLING FREQUENCY)ArchitectureFiltersRF/IF(MHz)fs(MHz)Gain(dB)NF(dB)ADC SNR/ENOB(dB)/-IIP3(dB)OP1dB(dB)IDCmARF SamplingRF Sampling