最新(4)异步FIFO电路设计源代码.docx
精品资料(4)异步FIFO电路设计源代码.FPGA电路设计FIFO源代码define ADDR_WIDTH 8 /地址位宽define DATA_WIDTH 8 /数据位宽define RAM_WIDTH 8 /RAM数据位宽define RAM_DEPTH 256 /RAM深度module fifo_test(clk_100M,/写时钟clk_5M, /读时钟rst_n,/ 全局复位信号wr_en,/ 写使能 低有效rd_en,/ 读使能 低有效wr_data,/8位数据输入rd_data,/8位数据输出wr_full,/ 写满标志 高有效rd_empty);/ 读空标志 高有效/输入信号 input clk_100M; input clk_5M; input rst_n; input wr_en; input rd_en; inputDATA_WIDTH-1:0 wr_data; output reg DATA_WIDTH-1:0 rd_data; output reg wr_full; output reg rd_empty; reg RAM_WIDTH-1:0 memRAM_DEPTH-1:0;/ 8位256单元regADDR_WIDTH-1:0 wr_addr; / 8位写地址 regADDR_WIDTH-1:0 rd_addr; / 8读地址reg rd_flag;reg wr_flag;/写地址产生逻辑 always (posedge clk_100M or negedge rst_n) begin if(!rst_n)beginwr_addr <= 8'h0;wr_flag <= 0;end else if(!wr_en)beginif(!wr_full && (rd_addr!=(wr_addr+1)beginwr_flag <= 1;wr_addr <= wr_addr + 1'b1;endelsewr_flag <= 0;end end/ 写数据产生逻辑 always (posedge clk_100M) begin if(!wr_en && !wr_full && wr_flag) memwr_addr <= wr_data; end/写满产生标志 always (posedge clk_100M or negedge rst_n) begin if(!rst_n)wr_full <= 0; else if(rd_addr = (wr_addr+1)wr_full <= 1'b1;elsewr_full <= 1'b0; end/读地址产生逻辑 always (posedge clk_5M or negedge rst_n) begin if(!rst_n)beginrd_flag <= 0;rd_addr <= 8'd0;end else if(!rd_en)beginif(!rd_empty && (wr_addr!=(rd_addr+1)beginrd_flag <= 1;rd_addr <= rd_addr + 1'b1;endelserd_flag <= 0;end end/读数据产生逻辑 always (posedge clk_5M) begin if(!rd_en && !rd_empty && rd_flag) rd_data <= memrd_addr; end/读空产生标志 always (posedge clk_5M or negedge rst_n) begin if(!rst_n)rd_empty <= 1'b1; else if(wr_addr = (rd_addr+1)|(wr_addr = rd_addr)rd_empty <= 1'b1;else rd_empty <= 1'b0; endendmodule/ 激励源代码：module fifo_test_IB; reg clk_100M;reg clk_5M; reg rst_n; / 全局复位信号 reg wr_en; / 写使能 reg rd_en; / 读使能 regDATA_WIDTH-1:0 wr_data; wire7:0 rd_data;wire wr_full;wire rd_empty;reg7:0 cnt;fifo_test fifo1(clk_100M,clk_5M, rst_n,wr_en,rd_en,wr_data,rd_data,wr_full,rd_empty);always #15 clk_5M = clk_5M; /读时钟always #5 clk_100M = !clk_100M; /写时钟initialbegin rst_n = 0; clk_100M = 0; clk_5M = 1; wr_en = 0; rd_en = 0; #25 rst_n = 1; endalways (posedge clk_100M or negedge rst_n)beginif(!rst_n)wr_data <= 8'd0;else wr_data <= cnt;endalways (posedge clk_100M or negedge rst_n)beginif(!rst_n)cnt <= 8'd38;else cnt <= cnt + 1'b1;endendmodule
