MIPI协议详细介绍.ppt

What is MIPI?What is MIPI?v MIPI stands for Mobile Industry Processor Interface MIPI Alliance is a collaboration of mobile industry leaders. Objective to promote open standards for interfaces to mobile application processors. Intends to speed deployment of new services to mobile users by establishing Spec.v Board Members in MIPI Alliance Intel, Motorola, Nokia, NXP,Samsung, ST, TIWhat is MIPI?What is MIPI?v MIPI Alliance Specification for display DCS (Display Command Set) DCS is a standardized command set intended for command mode display modules. DBI, DPI (Display Bus Interface, Display Pixel Interface) DBI：Parallel interfaces to display modules having display controllers and frame buffers. DPI：Parallel interfaces to display modules without on-panel display controller or frame buffer. DSI, CSI (Display Serial Interface, Camera Serial Interface) DSI specifies a high-speed serial interface between a host processor and display module. CSI specifies a high-speed serial interface between a host processor and camera module. D-PHY D-PHY provides the physical layer definition for DSI and CSI.DSI LayersDSI LayersDCS specDSI specD-PHY specOutlineOutlinevD-PHY Introduction Lane Module, State and Line levels Operating Modes Escape Mode System Power States Electrical Characteristics SummaryIntroduction for D-PHYv D-PHY describes a source synchronous, high speed, low power, low cost PHYv A PHY configuration containsA Clock LaneOne or more Data Lanesv Three main lane typesUnidirectional Clock LaneUnidirectional Data LaneBi-directional Data Lanev Transmission ModeLow-Power signaling mode for control purpose：10MHz (max)High-Speed signaling mode for fast-data traffic：80Mbps 1Gbps per Lanev D-PHY low-level protocol specifies a minimum data unit of one byteA transmitter shall send data LSB first, MSB last.v D-PHY suited for mobile applicationsDSI：Display Serial InterfaceA clock lane, One to four data lanes.CSI：Camera Serial InterfaceTwo Data Lane PHY ConfigurationTwo Data Lane PHY ConfigurationLane Modulev PHY consists of D-PHY (Lane Module)v D-PHY may contain Low-Power Transmitter (LP-TX) Low-Power Receiver (LP-RX) High-Speed Transmitter (HS-TX) High-Speed Receiver (HS-RX) Low-Power Contention Detector (LP-CD)v Three main lane types Unidirectional Clock Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Unidirectional Data Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Bi-directional Data Lane Master, Slave：HS-TX, HS-RX,LP-TX, LP-RX, LP-CDUniversal Lane Module ArchitectureUniversal Lane Module ArchitectureLane States and Line Levels The two LP-TXs drive the two Lines of a Lane independently and single-ended. Four possible Low-Power Lane states (LP-00, LP-01, LP-10, LP-11) A HS-TX drives the Lane differentially. Two possible High Speed Lane states (HS-0, HS-1) During HS transmission the LP Receivers observe LP-00 on the Lines Line Levels (typical) LP：01.2V HS：100300mV (Swing：200mV) Lane States LP-00, LP-01, LP-10, LP-11 HS-0, HS-1Operating Modes There are three operating modes in Data Lane Escape mode, High-Speed (Burst) mode and Control mode Possible events starting from the Stop State of control mode Escape mode request (LP-11LP-10LP-00LP-01LP-00) High-Speed mode request (LP-11LP-01LP-00) Turnaround request (LP-11LP-10LP-00LP-10LP-00)Escape ModeEscape Modev Escape mode is a special operation for Data Lanes using LP states. With this mode some additional functionality becomes available：LPDT, ULPS, Trigger A Data Lane shall enter Escape mode via LP-11LP-10LP-00LP-01LP-00 Once Escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested action. Escape mode uses Spaced-One-Hot Encoding. means each Mark State is interleaved with a Space State (LP-00). Send Mark-0/1 followed by a Space to transmit a zero-bit/ one-bit A Data Lane shall exit Escape mode via LP-10LP-11v Ultra-Low Power State During this state, the Lines are in the Space state (LP-00) Exited by means of a Mark-1 state with a length TWAKEUP(1ms) followed by a Stop state.Escape ModeEscape ModeClock Lane Ultra-Low Power StateClock Lane Ultra-Low Power Statev A Clock Lane shall enter ULPS via LP-11LP-10LP-00v exited by means of a Mark-1 with a length TWAKEUP followed by a Stop State LP-10 TWAKEUP LP-11 The minimum value of TWAKEUP is 1msHigh-Speed Data TransmissionHigh-Speed Data Transmissionv The action of sending high-speed serial data is called HS transmission or burst.v Start-of-Transmission LP-11LP-01LP-00SoT(0001_1101) HS Data Transmission Burst All Lanes will start synchronously But may end at different times The clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave sidev End-of-Transmission H Toggles differential state immediately after last payload data bitv and keeps that state for a time THS-TRAILHigh-Speed Clock TransmissionHigh-Speed Clock Transmissionv Switching the Clock Lane between Clock Transmission and LP Mode A Clock Lane is a unidirectional Lane from Master to Slave In HS mode, the clock Lane provides a low-swing, differential DDR clock signal. the Clock Burst always starts and ends with an HS-0 state. the Clock Burst always contains an even number of transitionsSummary for D-PHYSummary for D-PHYv Lane Module, Lane State and Line LevelsLane Module：LP-TX, LP-RX, HS-TX, HS-RX, LP-CDLane States：LP-00, LP-01, LP-10, LP-11, HS-0, HS-1Line Levels (typical)：LP：01.2V, HS：100300mV (Swing：200mV)vOperating ModesEscape Mode entry procedure ：LP-11LP-10LP-00LP-01LP-00Entry Code LPD (10MHz)Escape Mode exit procedure：LP-10LP-11High Speed Mode entry procedure：LP-11LP-01LP-00SoT(00011101) HSD (80Mbps 1Gbps)High Speed Mode exit procedure：EoTLP-11Control Mode - BTA transmission procedure：LP-11LP-10LP-00LP-10LP-00Control Mode - BTA receive procedure：LP-00LP-10LP-11vSystem Power StatesLow-Power mode, High-Speed mode, Ultra-Low Power modevFault DetectionContention Detection (LP-CD), Watchdog Timer, Sequence Error Detection (Error Report)vGlobal Operation Timing ParameterClock Lane Timing, Data Lane TimingOther Timing Initialization, BTA, Wake-Up from ULPSvElectrical CharacteristicsHS-RX, LP-RX, LP-TX, LP-CD, Pin characteristic, Clock signal, Data-Clock timingDC and AC characteristicOutlineOutlinev DSI Introduction Lane Distributor/Merger Conceptual Packet Structure Data Transmission Way Processor-Sourced Packets Peripheral-Sourced Packets Reverse-Direction LP Transmission Video Mode SummaryIntroduction for DSIIntroduction for DSIv DSI is a Lane-scalable interface for increased performance.One Clock Lane / One to Four Data LanesvDSI-compliant peripherals support either of two basic modes of operationCommand Mode (Similar to MPU IF)Data Lane 0：bidirectionalFor returning data, ACK or error report to hostAdditional Data Lanes：unidirectional.Video Mode (Similar to RGB IF)Data Lane 0：bidirectional or unidirectional;Additional Data Lanes：unidirectional.Video data should only be transmitted using HS mode.vTransmission ModeHigh-Speed signaling modeLow-Power signaling modeForward/Reverse direction LP transmissions shall use Data Lane 0 onlyFor returning data, DSI-compliant systems shall only use Data Lane 0 in LP ModevPacket TypesShort Packet：4 bytes (fixed length)Long Packet：665541 bytes (variable length)Two Data Lanes HS Transmission ExampleTwo Data Lanes HS Transmission ExampleData Transmission Wayv Separate Transmissionsv Separate Transmissionsv KEY:LPS Low Power State SP Short PacketSoT Start of Transmission LgP Long PacketEoT End of TransmissionShort Packet StructureShort Packet Structurev Packet Header (4 bytes)Data Identifier (DI) * 1byte： Contains the Virtual Channel7:6 and Data Type5:0.Packet Data * 2byte：Length is fixed at two bytesError Correction Code (ECC) * 1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.v Packet SizeFixed length 4 bytesv The first byte of any packet is the DI (Data Identifier) byte.DI7:6：These two bits identify the data as directed to one of four virtual channels.DI5:0：These six bits specify the Data Type.Long Packet StructureLong Packet StructurevPacket Header (4 bytes)Data Identifier (DI) * 1byte：Contains the Virtual Channel7:6 and Data Type5:0.Word Count (WC) * 2byte：defines the number of bytes in the Data Payload.Error Correction Code (ECC) * 1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.vData Payload (065535 bytes)Length = WC bytesvPacket Footer (2 bytes)：ChecksumIf the payload has length 0, then the Checksum calculation results in FFFFhIf the Checksum isnt calculated, the Checksum value is 0000hvPacket Size4 + (065535) + 2 = 6 65541 bytesData Types for Processor-sourced PacketsData Types for Processor-sourced PacketsError Correction CodeError Correction Codev P7 = 0v P6 = 0v P5 = D10D11D12D13D14D15D16D17D18D19D21D22D23v P4 = D4D5D6D7D8D9D16D17D18D19D20D22D23v P3 = D1D2D3D7D8D9D13D14D15D19D20D21D23v P2 = D0D2D3D5D6D9D11D12D15D18D20D21D22v P1 = D0D1D3D4D6D8D10D12D14D17D20D21D22D23v P0 = D0D1D2D4D5D7D10D11D13D16D20D21D22D23ChecksumChecksumvunsigned char xx = 0 x01,0 x5a,0 x5a,0 x03,0 x08,0 x2A, 0 x00,0 x01 ,0 x00,0 xF8,0 x00,0 xF6,0 x57,0 x00,0X00,0 xE5;vtypedef unsigned short U16;vtypedef unsigned char U8;vU16 CRC_test;vU16 crc16_update(U16 crc, U8 a);vint main()vv U16 crc,i;v crc = 0 xFFFF;v for (i=0; i1; i+) crc = crc16_update(crc, xxi);v CRC_test = crc;v vU16 crc16_update(U16 crc, U8 a) vv int i;v crc =a;v for (i = 0; i 1) 0 x8408;v else crc = (crc 1);v v return crc;vPeripheral-to-Processor LP TransmissionsvDetailed format descriptionPacket structure for peripheral-to-processor transactions is the same as forthe processor-to-peripheral directionv For a single-byte read response, valid data shall be returned in the first byte The second byte shall be sent as 00hvIf the peripheral does not support Checksum it shall return 0000hPeripheral-to-Processor LP Transmissionsv Peripheral-to-processor transactions are of four basic types Tearing Effect (TE)：trigger message (BAh) Acknowledge：trigger message (84h) Acknowledge and Error Report：short packet (Data Type is 02h) Response to Read Request：short packet or long packet Generic Read Response、DCS Read Response（1byte, 2byte, multi byte）v Feature BTA shall take place after every peripheral-to-processor transaction Multi-Lane systems shall use Lane 0 for all peripheral-to-processor transmissions Reverse-direction signaling shall only use LP mode of transmissionVideo Modev DSI supports three formats for Video Mode data transmission Non-Burst Mode with Sync Pulses Non-Burst Mode with Sync Events Burst ModeSummary for DSIv DSI is a Lane-scalable interface.One Clock LaneOne to Four Data Lanesv Transmission ModeHigh-Speed signaling mode (differential signal) (100mV300mV)Low-Power signaling mode (single-ended signal) (0V1.2V)For returning data, only use Data Lane 0 in LP Modev Packet TypesShort Packet：4 bytes (fixed length)Data ID (1byte) + Data0 (1byte) + Data1 (1byte) + ECC (1byte)Long Packet：665541 bytes (variable length)Packet Header (4 bytes) + Data Payload (065535 bytes) + Packet Footer (2 bytes)v Operation ModeCommand Mode (Similar to MPU IF)Video Mode (Similar to RGB IF)Non-Burst Mode with Sync PulsesNon-Burst Mode with Sync EventsBurst Mode Thank you!结束结束