整理版EDA技术与VHDL第三章课后习题答案第3版潘松黄继业.docx
第3章 VHDL基础 3-1：画出与下例实体描述对应的原理图符号元件：ENTITY buf3s IS - 实体1：三态缓冲器PORT (input : IN STD_LOGIC ; - 输入端enable : IN STD_LOGIC ; - 使能端output : OUT STD_LOGIC ) ; - 输出端END buf3x ;ENTITY mux21 IS -实体2： 2 选1 多路选择器PORT (in0, in1, sel : IN STD_LOGIC;output : OUT STD_LOGIC);3-1.答案3-2. 图3-30 所示的是4 选1 多路选择器，试分别用IF_THEN 语句与CASE 语句的表达方式写出此电路的VHDL 程序。选择限制的信号s1 与s0 的数据类型为STD_LOGIC_VECTOR；当s1='0'，s0='0'；s1='0'，s0='1'；s1='1'，s0='0'与s1='1'，s0='1'分别执行y<=a, y<=b, y<=c, y<=d。3-2.答案LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41 ISPORT(s:IN STD_LOGIC_VECTOR(1 DOWNTO 0); -输入选择信号a,b,c,d:IN STD_LOGIC; -输入信号y:OUT STD_LOGIC);-输出端END ENTITY;ARCHITECTURE ART OF MUX41 ISBEGINPROCESS(s)BEGINIF (S="00") THEN y<=a;ELSIF (S="01") TH EN y<=b;ELSIF (S="10") TH EN y<=c;ELSIF (S="11") TH EN y<=d;ELSE y<=NULL;END IF;EDN PROCESS;END ART;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41 ISPORT(s:IN STD_LOGIC_VECTOR(1 DOWNTO 0); -输入选择信号a,b,c,d:IN STD_LOGIC; -输入信号y:OUT STD_LOGIC);-输出端END MUX41;ARCHITECTURE ART OF MUX41 ISBEGINPROCESS(s)BEGINCASE s ISWHEN “00” => y<=a;WHEN “01” => y<=b;WHEN “10” => y<=c;WHEN “11” => y<=d;WHEN OTHERS =>NULL;END CASE;END PROCESS;END ART;3-3. 图3-31 所示的是双2 选1 多路选择器构成的电路MUXK，对于其中MUX21A，当s='0'与'1'时，分别有y<='a'与y<='b'。试在一个结构体中用两个进程来表达此电路，每个进程中用CASE 语句描述一个2 选1 多路选择器MUX21A。3-3.答案LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX221 ISPORT(a1,a2,a3:IN STD_LOGIC_VECTOR(1 DOWNTO 0); -输入信号s0,s1:IN STD_LOGIC;outy:OUT STD_LOGIC);-输出端END ENTITY;ARCHITECTURE ONE OF MUX221 ISSIGNAL tmp : STD_LOGIC;BEGINPR01:PROCESS(s0)BEGINIF s0=”0” THEN tmp<=a2;ELSE tmp<=a3;END IF;END PROCESS;PR02:PROCESS(s1)BEGINIF s1=”0” THEN outy<=a1;ELSE outy<=tmp;END IF;END PROCESS;END ARCHITECTURE ONE;END CASE;3-4.下图是一个含有上升沿触发的D 触发器的时序电路，试写出此电路的VHDL 设计文件。3-4.答案LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MULTI ISPORT(CL:IN STD_LOGIC; -输入选择信号CLK0:IN STD_LOGIC; -输入信号OUT1:OUT STD_LOGIC);-输出端END ENTITY;ARCHITECTURE ONE OF MULTI ISSIGNAL Q : STD_LOGIC;BEGINPR01: PROCESS(CLK0)BEGINIF CLK EVENT AND CLK=1THEN Q<=NOT(CL OR Q);ELSEEND IF;END PROCESS;PR02: PROCESS(CLK0)BEGINOUT1<=Q;END PROCESS;END ARCHITECTURE ONE;END PROCESS;3-5.给出1 位全减器的VHDL 描述。要求：(1) 首先设计1 位半减器，然后用例化语句将它们连接起来，图3-32 中h_suber 是半减器，diff 是输出差，s_out 是借位输出，sub_in 是借位输入。(2) 以1 位全减器为基本硬件，构成串行借位的8 位减法器，要求用例化语句来完成此项设计(减法运算是x y - sun_in = diffr)3-5.答案底层文件1：or2a.VHD 实现或门操作LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY or2a ISPORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY or2a;ARCHITECTURE one OF or2a ISBEGINc <= a OR b;END ARCHITECTURE one;底层文件2：h_subber.VHD 实现一位半减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY h_subber ISPORT(x,y:IN STD_LOGIC;diff,s_out:OUT STD_LOGIC);END ENTITY h_subber;ARCHITECTURE ONE OF h_subber ISSIGNAL xyz: STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINxyz <= x & y;PROCESS(xyz)BEGINCASE xyz ISWHEN "00" => diff<='0's_out<='0'WHEN "01" => diff<='1's_out<='1'WHEN "10" => diff<='1's_out<='0'WHEN "11" => diff<='0's_out<='0'WHEN OTHERS => NULL;END CASE;END PROCESS;END ARCHITECTURE ONE;顶层文件：f_subber.VHD 实现一位全减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY f_subber ISPORT(x,y,sub_in:IN STD_LOGIC;diffr,sub_out:OUT STD_LOGIC);END ENTITY f_subber;ARCHITECTURE ONE OF f_subber ISCOMPONENT h_subberPORT(x,y:IN STD_LOGIC;diff,S_out:OUT STD_LOGIC);END COMPONENT;COMPONENT or2aPORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END COMPONENT;SIGNAL d,e,f: STD_LOGIC;BEGINu1: h_subber PORT MAP(x=>x,y=>y,diff=>d,s_out=>e);u2: h_subber PORT MAP(x=>d,y=>sub_in,diff=>diffr,s_out=>f);u3: or2a PORT MAP(a=>f,b=>e,c=>sub_out);END ARCHITECTURE ONE;END ARCHITECTURE ART;3-6.依据下图，写出顶层文件MX3256.VHD 的VHDL 设计文件。3-6.答案MAX3256 顶层文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MAX3256 ISPORT (INA,INB,INCK: IN STD_LOGIC;INC: IN STD_LOGIC;E,OUT:OUT STD_LOGIC);END ENTITY MAX3256;ARCHITECTURE ONE OF MAX3256 ISCOMPONENT LK35 -调用LK35 声明语句PORT(A1,A2:IN STD_LOGIC;CLK:IN STD_LOGIC;Q1,Q2:OUT STD_LOGIC);END COMPONENT;COMPONENT D -调用D 触发器声明语句PORT(D,C:IN STD_LOGIC;CLK:IN STD_LOGIC;Q:OUT STD_LOGIC);END COMPONENT;COMPONENT MUX21-调用二选一选择器声明语句PORT(B,A:IN STD_LOGIC;S:IN STD_LOGIC;C:OUT STD_LOGIC);END COMPONENT;SIGNAL AA,BB,CC,DD: STD_LOGIC;BEGINu1: LK35 PORT MAP(A1=>INA,A2=>INB,CLK=INCK, Q1=>AA,Q2=>BB);u2: D PORT MAP(D=>BB;CLK=>INCK,C=>INC,Q=>CC);u3: LK35 PORT MAP (A1=>BB,A2=>CC,CLK=INCK, Q1=>DD,Q2=>OUT1)；u4: MUX21 PORT MAP (B=>AA,A=>DD,S=>BB,C=>E);END ARCHITECTURE ONE;3-7设计含有异步清零与计数使能的16 位二进制加减可控计数器。3-7.答案：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT16 ISPORT(CLK,RST,EN:IN STD_LOGIC;CHOOSE:IN BIT;SETDATA:BUFFER INTEGER RANCE 65535 DOWNTO 0;COUT: BUFFER INTEGER RANCE 65535 DOWNTO 0);END CNT16;ARCHITECTURE ONE OF CNT16 ISBEGINPROCESS(CLK,RST,SDATA)VARIABLE QI:STD_LOGIC_VECTOR(65535 DOWNTO 0);BEGINIF RST='1' THEN -计数器异步复位QI:=(OTHERS=>'0');ELSIF SET=1 THEN-计数器一步置位QI:=SETDATA;ELSIF CLK'EVENT AND CLK='1' THEN -检测时钟上升沿IF EN=1 THEN 检测是否允许计数IF CHOOSE=1 THEN -选择加法计数QI:=QI+1; -计数器加一ELSE QI=QI-1; -计数器加一END IF;END IF;END IF;COUT<=QI;-将计数值向端口输出END PROCESS;END ONE;3-13 程序1： SIGNAL A,EN : STD_LOGIC ; PROCESS ( A, EN ) VARIABLE B : STD_LOGIC ; BEGIN IF EN = 1 THEN B := A ; END IF ; END PROCESS ; 程序2： ARCHITECTURE one OF sample IS VARIABLE a,b,c : BEGIN c := a+b ; END ARCHITECTURE one ; 程序3： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( a,b : IN STD_LOGIC ; sel : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN IF sel = 0 THEN c<=a ; ELSE c<=b ; END IF ; END ARCHITECTURE one ; 6-1 什么是固有延时什么是惯性延时P150151答：固有延时(Inertial Delay)也称为惯性延时，固有延时的主要物理机制是分布电容效应。第 9 页
