verilog_简单交通灯实现(13页).doc
-简易交通控制器一、 设计要求设计一个交通控制器，用LED显示灯来表示交通状态，并以七段数码管显示器显示当前状态剩余秒数，具体要求如下：1、 主干道绿灯亮时，支干道红灯亮，反之依然，二者交替允许通过；主干道每次放行35s，支干道25s；每次由绿灯变为红灯过程中，黄灯亮作为过度，黄灯亮5s；2、 能实现正常的倒计时显示功能；3、 能实现总体清零功能，计数器由初始状态开始计数，对应状态的指示灯亮；4、 能实现特殊状态的功能的显示，进入特殊状态时，东西、南北均显示红灯状态；二、 设计原理图三、 程序如下module jiao_tong(clk,jin,ra,ya,ga,rb,yb,gb,seg7,scan);input clk,jin;output ra,ya,ga,rb,yb,gb;output7:0 scan;output7:0 seg7;reg ra,ya,ga,rb,yb,gb;reg7:0 scan;reg7:0 seg7;reg1:0 state,next_state;parameter state0=2'b00,state1=2'b01,state2=2'b10,state3=2'b11;reg clk1khz,clk1hz;reg3:0 one,ten;reg1:0 cnt;reg3:0 data;reg7:0 seg7_temp;reg r1,r2,g1,g2,y1,y2;reg14:0 count1;reg8:0 count2;reg a;reg3:0 qh,ql;initial scan<=8'b00000000;always (posedge clk)beginif(count1='d25000)begin clk1khz<=clk1khz;count1<=0;endelsebegin count1<=count1+1'b1;endend always (posedge clk1khz)begin if(count2='d500)begin clk1hz<=clk1hz;count2<=0;endelsebegin count2<=count2+1'b1;endendalways (posedge clk1hz)beginstate=next_state;case(state)state0:beginif(jin)beginif(!a)begin qh<='b0011;ql<='b0101;a<=1; r1<=0;y1<=0;g1<=1; r2=1;y2<=0;g2<=0;endelsebegin if(!qh&&!ql) begin next_state<=state1;a<=0; qh<='b0000;ql<='b0000; end else if(!ql) begin ql<='b1001;qh<=qh-1'b1; end else begin ql<=ql-1'b1; end end end endstate1:beginif(jin)beginif(!a)begin qh<='b0000;ql<='b0101;a<=1; r1<=0;y1<=1;g1<=0; r2=1;y2<=0;g2<=0;endelse beginif(!ql)begin next_state<=state2;a<=0;qh<='b0000;ql<='b0000;endelse begin ql<=ql-1'b1;endendend endstate2:begin if(jin)beginif(!a)begin qh<='b0010;ql<='b0101;a<=1; r1<=1;y1<=0;g1<=0; r2=0;y2<=0;g2<=1;endelsebegin if(!qh&&!ql) begin next_state<=state3;a<=0; qh<='b0000;ql<='b0000; end else if(!ql) begin ql<='b1001;qh<=qh-1'b1; end else begin ql<=ql-1'b1; end end end endstate3:beginif(jin)beginif(!a)begin qh<='b0000;ql<='b0101;a<=1; r1<=1;y1<=0;g1<=0; r2=0;y2<=1;g2<=0;endelse beginif(!ql)begin next_state<=state0;a<=0;qh<='b0000;ql<='b0000;endelse begin ql<=ql-1'b1;endendend endendcaseone<=ql;ten<=qh;end/-always (jin,clk1hz,r1,r2,g1,g2,y1,y2,seg7_temp)beginif(!jin)begin ra<=r1|jin;rb<=r2|jin; ga<=g1&&jin; gb<=g2&&jin; ya<=y1&&jin; yb<=y2&&jin; seg70<=seg7_temp0|clk1hz; seg71<=seg7_temp1|clk1hz; seg72<=seg7_temp2|clk1hz; seg73<=seg7_temp3|clk1hz; seg74<=seg7_temp4|clk1hz; seg75<=seg7_temp5|clk1hz; seg76<=seg7_temp6|clk1hz; seg77<=seg7_temp7|clk1hz; end else begin seg77:0<=seg7_temp7:0; ra<=r1;rb<=r2;ga<=g1;gb<=g2;ya<=y1;yb<=y2;endend/-always (posedge clk1khz)begin if(cnt='b01)begin cnt<='b00;endelse begin cnt<=cnt+1'b1; endendalways (cnt,one,ten)begincase(cnt)'b00 : begin data3:0<=ten;scan<='b01111111;end'b01 : begin data3:0<=one;scan<='b10111111;enddefault : begin data3:0<='bx;scan<='bx;endendcaseendalways (data)begincase(data3:0)4'b0000 : seg7_temp7:0<=8'b11000000;4'b0001 : seg7_temp7:0<=8'b11111001;4'b0010 : seg7_temp7:0<=8'b10100100;4'b0011 : seg7_temp7:0<=8'b10110000;4'b0100 : seg7_temp7:0<=8'b10011001;4'b0101 : seg7_temp7:0<=8'b10010010;4'b0110 : seg7_temp7:0<=8'b10000010;4'b0111 : seg7_temp7:0<=8'b11111000;4'b1000 : seg7_temp7:0<=8'b10000000;4'b1001 : seg7_temp7:0<=8'b10010000;default : seg7_temp7:0<=8'b10000110;endcaseendendmodule 第 14 页-
