verilog数字钟代码(7页).doc

-verilog数字钟代码-第 7 页module digclk(clk,en,rst,dula,wela,s1,s2,s3,led,flag1,start1,flag2,start2,aled,s6,s4,s5); /s1调时 s2调分 s3调秒 wela位码 dula段码 en使能 clk时钟,flag1是跑表标志（拨上去就是显示跑表），置一为跑表功能,start1为跑表开始停止/flag2为闹钟标志（拨上去就是设置闹钟时间） start2为闹钟开关 aled闹钟提示灯input clk,rst,en,s1,s2,s3,flag1,start1,flag2,start2,s6,s4,s5;output 2:0 wela;output 7:0 dula;output led;output aled;reg led;reg aled;reg 7:0 cnt,dula;reg 2:0 wela;reg7:0 hourh,hourl,minh,minl,sech,secl;reg7:0 phourh,phourl,pminh,pminl,psech,psecl;reg7:0 ahourh,ahourl,aminh,aminl,asech,asecl;reg3:0 a; /a用于数码管显示的临时变量(* synthesis, keep *) reg clk1;always (posedge clk1)beginif(start2)beginif(hourh=ahourh&&hourl=ahourl&&minh=aminh&&minl=aminl&&sech=asech&&secl=asecl) aled=1'b1;else aled=1'b0;endendalways (posedge clk1) /闹钟功能beginif(flag2)beginif(!s4) /调节小时 begin /*if(ahourl=9)begin ahourl<=0;ahourh<=ahourh+1;end if(ahourh=2&&ahourl=3)begin ahourh<=0;ahourl<=0; end else ahourl<=ahourl+1;*/ ahourl<=ahourl+1; if(ahourl=3&&ahourh=2)begin ahourl<=0;ahourh<=0;end if(ahourl=9) begin ahourl<=0;ahourh<=ahourh+1;end; endelse if(!s5) /调节分钟 begin if(aminl=9) begin aminl<=0; if(aminh=5) aminh<=0; else aminh<=aminh+1; end else aminl<=aminl+1; endelse if(!s6) /调节秒钟（调节都是在暂停的前提下）beginif(asecl=9)beginasecl<=0;if(asech=5) asech<=0;else asech<=asech+1;endelse asecl<=asecl+1; endendendalways (posedge clk1)/用于跑表beginif(flag1&&start1)beginif(psecl=9) /时钟正常跳动状态 begin psecl<=0; if(psech=5) begin psech<=0; if(pminl=9) begin pminl<=0; if(pminh=5) begin pminh<=0; if(phourl=9) begin phourl<=0;phourh<=phourh+1;end else if(phourh=2&&phourl=3) begin phourl<=0; phourh<=0;end else phourl<=phourl+1; end else pminh<=pminh+1; end else pminl<=pminl+1; end else psech<=psech+1; endelse psecl<=psecl+1;endelse if(!flag1) begin psecl<=0;psech<=0;pminl<=0;pminh<=0;phourl<=0;phourh<=0; endendalways (posedge clk)/用于分频begincnt=cnt+1;if(cnt=200) begin clk1=1'b1; cnt=0; endelse clk1=1'b0; /200分频，CLK为数码管扫描频率，CLK1为计数频率if(wela<7) wela=wela+1; else wela=0;endalways (posedge clk1)/整点报时beginif(minh=0&&minl=0&&sech=0&&secl=0)led=1'b1;else led=1'b0;endalways (posedge clk1 or negedge rst) /这里负责处理使能和复位 暂停调时 使能处于开的时候则是正常显示beginif(!rst) begin secl<=0;sech<=0;minl<=0;minh<=0;hourl<=0;hourh<=0; endelse if(!en) /时钟暂停，开始调时beginif(!s1) /调节小时 begin /*if(hourh=2&&hourl=4)begin hourl<=0;hourh<=0; end else if(hourl=9)begin hourl<=0;hourh<=hourh+1;end else hourl<=hourl+1;*/ hourl<=hourl+1; if(hourl=3&&hourh=2)begin hourl<=0;hourh<=0;end if(hourl=9) begin hourl<=0;hourh<=hourh+1;end; end else if(!s2) /调节分钟 begin if(minl=9) begin minl<=0; if(minh=5) minh<=0; else minh<=minh+1; end else minl<=minl+1; endelse if(!s3) /调节秒钟（调节都是在暂停的前提下）beginif(secl=9)beginsecl<=0;if(sech=5) sech<=0;else sech=sech+1;endelse secl<=secl+1;end end else if(secl=9) /时钟正常跳动状态 begin secl<=0; if(sech=5) begin sech<=0; if(minl=9) begin minl<=0; if(minh=5) begin minh<=0; if(hourl=9) begin hourl<=0;hourh<=hourh+1;end else if(hourh=2&&hourl=3) begin hourl<=0; hourh<=0;end else hourl<=hourl+1; end else minh<=minh+1; end else minl<=minl+1; end else sech<=sech+1; end else secl<=secl+1;endalways (wela)/用于数码管显示beginif(flag1&&!flag2)begin case(wela)0:a=phourh;1:a=phourl;2:a=12;3:a=pminh;4:a=pminl;5:a=12;6:a=psech;7:a=psecl;default: a=0;endcasecase(a)0:dula<=8'b00111111; 1:dula<=8'b00000110;2:dula<=8'b01011011; 3:dula<=8'b01001111; 4:dula<=8'b01100110; 5:dula<=8'b01101101;6:dula<=8'b01111101; 7:dula<=8'b00000111; 8:dula<=8'b01111111; 9:dula<=8'b01101111; /8段译码值 是倒着看的12:dula<=8'b01000000;default:dula<=8'b11111111;endcaseendelse if(flag2&&!flag1)begincase(wela)0:a=ahourh;1:a=ahourl;2:a=12;3:a=aminh;4:a=aminl;5:a=12;6:a=asech;7:a=asecl;default: a=0;endcasecase(a)0:dula<=8'b00111111; 1:dula<=8'b00000110;2:dula<=8'b01011011; 3:dula<=8'b01001111; 4:dula<=8'b01100110; 5:dula<=8'b01101101;6:dula<=8'b01111101; 7:dula<=8'b00000111; 8:dula<=8'b01111111; 9:dula<=8'b01101111; /8段译码值12:dula<=8'b01000000;default:dula<=8'b11111111;endcaseendelse begincase(wela)0:a=hourh;1:a=hourl;2:a=12;3:a=minh;4:a=minl;5:a=12;6:a=sech;7:a=secl;default: a=0;endcasecase(a)0:dula<=8'b00111111; 1:dula<=8'b00000110;2:dula<=8'b01011011; 3:dula<=8'b01001111; 4:dula<=8'b01100110; 5:dula<=8'b01101101;6:dula<=8'b01111101; 7:dula<=8'b00000111; 8:dula<=8'b01111111; 9:dula<=8'b01101111; /8段译码值12:dula<=8'b01000000;default:dula<=8'b11111111;endcaseendendendmodule