VerilogHDL代码_AHB总线_master部分(9页).doc
-VerilogHDL代码_AHB总线_master部分-第 9 页module ahb_master (HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,hcount,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA);output HBUSREQ,HLOCK,HWRITE;output 1:0HTRANS,HSEL;output 31:0HADDR,HWDATA;output 2:0HSIZE,HBURST;input HGRANT,HREADY,HCLK,HRESETn,BUSREQ,ADDREQ,WRITE;input 31:0ADDE,WDATA;input 2:0SIZE,BURST;input 1:0HRESP,SEL,TRANS;input 31:0HRDATA;reg HBUSRREQ,HLOCK,HWRITE,hcount;reg 1:0HTRANS,HSEL;reg 31:0HADDR,HWDATA;reg 2:0HSIZE,HBURST;wire HGRANT,HREADY,HCLK,HRESETn,WRITE;wire 31:0ADDR,WDATA;wire 2:0SIZE,BURST;wire 1:0HRESP,SEL,TRANS;wire 31:0HRDATA;reg bus_reg,adde_reg,new_hready,old_hready;reg 31:0RDATA;reg 31:0h_addr;parameter OKAY=2'b00 ERROR=2'b01 RETRY=2'b10 SPLIT=2'b11;always (posedge HCLK)begin if(!HRESETn) begin HBUSREQ=0; HLOCK=0; HWRITE=0; HTRANS=2'b00; HSEL=2'b00; HADDR=32'h000000000; HWDATA=32'h000000000; HSIZE=2'b00; HBURST=2'b00; bus_reg=0; addr_reg=0; new_hready=0; old_hready=0; hcount=0; endend always (posedge HCLK)begin if(HRESETn) begin if(!addr_reg) begin if(ADDREQ) begin HADDR=ADDR; h_addr=ADDR; HWRITE=WRITE; HSIZE=SIZE; HBURST=BURST; HSEL=SEL; HTRANS=TRANS; addr_reg=1'b1; HWDATA=32'h000000000; end end else if(addr_reg) begin HADDR=32'h000000000; HWRITE=1'b0; HSIZE=3'b000; HBURST=3'b000; HTRANS=2'b00; addr_reg=1'b0; end if(!ADDREQ) begin if(WRITE) begin hcount=0; case(TRANS) 2'b00:begin HWDATA=WDATA; if(HREADY && !new_hready && HRESP=ERROR) new_hready=1; else if(new_hready!=old_hready) HWDATA=32'h00000000; end 2'b01:begin hcount=hcount+1; new_hready=0; HWDATA=WDATA; if(HREADY &&!new_hready && HRESP) new_hready=1; else if(new_hready!=old hready) hWDATA=32'h00000000; end 2'b10:begin HWDATA=32'h00000000; end 2'b11:begin hcount=hcount+1; HWDATA=WDATA; if(HREADY && HRESP=OKAY) begin if(!new_hready) new_hready=1; end else if(new_hready!=old_hready) begin HWDATA=WDATA; new_hready=0; end else if(HREADY && HRESP=ERROR) begin HWDATA=32'h00000000; end end endcaseend else if(!WRITE) begin case(TRANS) 2'b00:begin if(!HREADY) RDATA=HRDATA; else if(HREADY) RDATA=32'h00000000; end 2'b01:begin if(!HREADY) begin RDATA=HRDATA; if(HBURST=000) h_addr=h_addr+1; else h_addr=h_addr-1; end else if(HREADY) RDATA=32'h00000000; end 2'b10:begin RDATA=32'h00000000; end 2'b11:begin if(!HREADY) begin RDATA=HRDATA; if(HBURST=000) h_addr=h_addr+1; else h_addr=h_addr-1; end endcase endendendendmodulemodule ram_top( HCLK , HRESETn , HSEL_s , HADDR_s , HBURST_s , HTRANS_s , HRDATA_s , HWDATA_s , HWRITE_s , HREADY_s , HRESP_sinput HCLK ;input HRESETn ;input HSEL_s ;input 19:0 HADDR_s ;input 2:0 HBURST_s ;input 1:0 HTRANS_s ;input 31:0 HWDATA_s ;input HWRITE_s ;output 1:0 HRESP_s ;output 31:0 HRDATA_s ;output HREADY_s ;wire 31:0 ram_RDATA ;wire 17:0 ram_ADDR ;wire 31:0 ram_WDATA ;wire ram_WRITE ;ram_ahbif U_ram_ahbif (.HCLK (HCLK ),.HRESETn (HRESETn ),.HSEL_s (HSEL_s ),.HADDR_s (HADDR_s ),.HBURST_s (HBURST_s ),.HTRANS_s (HTRANS_s ),.HRDATA_s (HRDATA_s ),.HWDATA_s (HWDATA_s ),.HWRITE_s (HWRITE_s ),.HREADY_s (HREADY_s ),.HRESP_s (HRESP_s ),.ram_RDATA (ram_RDATA ),.ram_ADDR (ram_ADDR ),.ram_WDATA (ram_WDATA ),.ram_WRITE (ram_WRITE )ram_infer U_ram_infer(.q (ram_RDATA ),.a (ram_ADDR ),.d (ram_WDATA ),.we (ram_WRITE ),.clk (HCLK )endmodulemodule ram_infer(q ,a ,d ,we ,clkoutput 31:0 q ;input 31:0 d ;input 17:0 a ;input we ;input clk ;reg 31:0 mem 262143:0 ;always (posedge clk) beginif (we) beginmema <= d;endendassign q = mema;endmodulemodule ram_ahbif(HCLK ,HRESETn ,HSEL_s ,HADDR_s ,HBURST_s ,HTRANS_s ,HRDATA_s ,HWDATA_s ,HWRITE_s ,HREADY_s ,HRESP_s ,ram_RDATA ,ram_ADDR ,ram_WDATA ,ram_WRITE/declaration of input & outputinput HCLK ;input HRESETn ;input HSEL_s ;input 19:0 HADDR_s ;input 2:0 HBURST_s ;input 1:0 HTRANS_s ;input 31:0 HWDATA_s ;input HWRITE_s ;output 1:0 HRESP_s ;output 31:0 HRDATA_s ;output HREADY_s ;input 31:0 ram_RDATA ;output 17:0 ram_ADDR ;output 31:0 ram_WDATA ;output ram_WRITE ;/declaration of registers & wires/wire 1:0 HRESP_s ;wire 31:0 HRDATA_s ;reg HREADY_s ;wire 31:0 ram_WDATA ;reg 17:0 ram_ADDR ;reg ram_WRITE ;wire wr_en ;wire rd_en ;wire ready_en ;/program & functionassign HRESP_s = 2'b00;always(posedge HCLK or negedge HRESETn)begin /HSIZE = 3'b010-32bitsif(!HRESETn) beginram_ADDR <= 18'b000000000000000000;end else if (HSEL_s = 1'b1) beginram_ADDR <= HADDR_s19:2;endendassign wr_en = HSEL_s & HTRANS_s1 & HWRITE_s;always(posedge HCLK or negedge HRESETn)beginif(!HRESETn) beginram_WRITE <= 1'b0;end else if(wr_en) beginram_WRITE <= 1'b1;end else beginram_WRITE <= 1'b0;endendassign ram_WDATA= HWDATA_s;assign HRDATA_s = ram_RDATA;assign ready_en = HSEL_s & HTRANS_s1;always(posedge HCLK or negedge HRESETn)beginif(!HRESETn) beginHREADY_s <= 1'b0;end else if(ready_en) beginHREADY_s <= 1'b1;end else beginHREADY_s <= 1'b0;endendendmodule
