现代电子技术综合实验-数字频率计设计实验报告(共28页).docx

精选优质文档-倾情为你奉上现代电子技术综合实验数字频率计设计实验报告姓名： 学号：一、系统总体设计设计要求1、被测输入信号：方波2、测试频率范围为：10Hz1MHz 扩展 1MHz 100MHz3、量程分为三档：第一档：闸门时间为1S时，最大读数为999.999KHz 第二档：闸门时间为0.1S时，最大读数为9999.99KHz 第三档：闸门时间为0.01S时，最大读数为99999.9KHz。4、显示工作方式：a、用六位BCD七段数码管显示读数。 b、采用记忆显示方法 c、实现对高位无意义零的消隐。系统工作原理信号的频率就是信号在单位时间内所产生的脉冲个数，其表达式为f=N/T，其中f为被测信号的频率，N为技术其所累计的脉冲个数，T为产生N个脉冲所需的时间。技术其所记录的结果，就是被测信号的频率。如在1s内记录1000个脉冲，则被测信号的频率为1000HZ。测量频率的基本方法有两种：计数法和计时法，或称测频法和测周期法。1、计数法计数法是将被测信号通过一个定时闸门加到计数器进行计数的方法，如果闸门打开的时间为T，计数器得到的计数值为N1，则被测频率为f=N1/T。改变时间T，则可改变测量频率范围。如图所示。计数法测量原理 设在T期间，计数器的精确计数值应为N,根据计数器的计数特性可知，N1的绝对误差是N1=N+1,N1的相对误差为N1=(N1-N)/N=1/N。由N1的相对误差可知，N的数值愈大，相对误差愈小，成反比关系。因此，在f以确定的条件下，为减少N的相对误差，可通过增大T的方法来降低测量误差。当T为某确定值时（通常取1s），则有f1=N1,而f=N，故有f1的相对误差：f1=(f1-f)/f=1/f 从上式可知f1的相对误差与f成反比关系，即信号频率越高，误差越小；而信号频率越低，则测量误差越大。因此测频法适合用于对高频信号的测量，频率越高，测量精度也越高。2、计时法计时法又称为测周期法，测周期法使用被测信号来控制闸门的开闭，而将标准时基脉冲通过闸门加到计数器，闸门在外信号的一个周期内打开，这样计数器得到的计数值就是标准时基脉冲外信号的周期值，然后求周期值的倒数，就得到所测频率值。首先把被测信号通过二分频，获得一个高电平时间是一个信号周期T的方波信号；然后用一个一直周期T1的高频方波信号作为计数脉冲，在一个信号周期T的时间内对T1信号进行计数，如图所示。计时法测量原理若在T时间内的计数值为N2,则有：T2=N2*T1 f2=1/T2=1/(N2*T1)=f1/N2 N2的绝对误差为N2=N+1。N2的相对误差为N2=(N2-N)/N=1/NT2的相对误差为T2=(T2-T)/T=(N2*T1-T)/T=f/f1从T2的相对误差可以看出，周期测量的误差与信号频率成正比，而与高频标准计数信号的频率成反比。当f1为常数时，被测信号频率越低，误差越小，测量精度也就越高。 根据本设计要求的性能与技术指标，首先需要确定能满足这些指标的频率测量方法。有上述频率测量原理与方法的讨论可知，计时法适合于对低频信号的测量，而计数法则适合于对较高频信号的测量。但由于用计时法所获得的信号周期数据，还需要求倒数运算才能得到信号频率，而求倒数运算用中小规模数字集成电路较难实现，因此，计时法不适合本实验要求。测频法的测量误差与信号频率成反比，信号频率越低，测量误差就越大，信号频率越高，其误差就越小。但用测频法所获得的测量数据，在闸门时间为一秒时，不需要进行任何换算，计数器所计数据就是信号频率。因此，本实验所用的频率测量方法是测频法。 单元电路的划分分频电路FPGA的石英振荡器，产生频率为48MHz的方波信号。因此需要分频电路，将48MHz的高频信号，分频为整个系统需要的信号：1Hz闸门信号和1KHz扫描显示信号计数器对外部输入的被测信号，进行计数锁存器对计数器的计数结果，进行锁存门控电路对计数电路、锁存电路，进行时序控制扫描显示控制电路对锁存的结果，进行动态扫描显示系统框图：二、单元电路设计单元电路设计思路一分频器分频器的功能是将提供的48MHz标准信号，产生所需的1Hz闸门控制信号及1KHz扫描时钟信号。因此通过计数器的计数，来实现分频器的功能例如：实现对一个信号的5分频if clkin'event and clkin = '1' then if cnt = 5 thencnt <= 1;clkout <=not clkout; elsecnt <= cnt + 1; end if; end if; 源程序见附录二计数器计数器的功能是对外部输入的被测信号，进行计数。因为系统要求，显示为6为数字，所以需要6位的计数器。因此采用6个10进制计数器级联的方法单级计数器级联后的计数器级联，分为同步级联和异步级联两种方式同步级联原理图：异步级联原理图：本设计选择的是同步级联源程序见附录三锁存器锁存器用来实现对6位计数结果，和溢出信号的锁存功能源程序见附录四门控电路门控电路的作用是对计数电路和锁存电路，进行时序控制例如：源程序见附录五扫描显示控制电路扫描显示控制电路的功能是对锁存的结果，进行动态扫描显示。选用频率1KHz的信号实现对六位已经锁存的计数结果的扫描输出 扫描显示控制电路分为以下几部分构成：1.计数部分：通过计数器的计数，来产生动态显示数码管的位选信号2.小数点控制部分：控制小数点的显示3.数据选择部分：根据计数部分产生的位选信号，来选择一组数据输出显示4.七段译码部分：将数据选择器输出的数据，进行译码，形成数码管的段选信号5.消隐部分实现高位无意义0的消隐各个部分间的链接关系如图：源程序见附录三、 设计实现顶层设计通过原件的声明，和原件的例化，来将各个底层实体，在顶层调用例如：architecture digitalfrequency_arch of digitalfrequency iscomponent fenpinPort ( clk : in STD_LOGIC; clkout1 : out STD_LOGIC; clkout1k : out STD_LOGIC);end component;beginu1:fenpin port map (clk24m,clk1,clk1k);end digitalfrequency_arch;管脚分配NET "overflow" LOC = K14;NET "clk24m" LOC = T8;NET "g" LOC = D7;NET "ledout<0>" LOC = A11;NET "ledout<1>" LOC = B12;NET "ledout<2>" LOC = A12;NET "ledout<3>" LOC = C12;NET "ledout<4>" LOC = C13;NET "ledout<5>" LOC = A13;NET "ledout<6>" LOC = B14;NET "digitalsignal" LOC = D14;NET "sel<0>" LOC = F8;NET "sel<1>" LOC = D8;NET "sel<2>" LOC = E7;NET "point" LOC = C11;下载过程 四、测试结果及结论测试结果输入信号为1MHz数码管显示为999.999KHz输入信号为10Hz数码管显示为0.010KHz输入信号为5000Hz数码管显示为5.000KHz输入信号为5555Hz数码管显示为5.555KHz输入为98429Hz数码管显示为98.429KHz实验结论当输入信号为1MHz时，显示稍有误差，其余量程范围内的信号均能精确显示，该数字频率计性能良好，实验成功！附录源程序1分频电路entity fenpin is Port ( clk : in STD_LOGIC; clkout1 : out STD_LOGIC; clkout1k : out STD_LOGIC);end fenpin;architecture Behavioral of fenpin issignal fcount1 :integer range 1 to 500:=1;signal fcount1k :integer range 1 to 24000:=1;signal clk1k:STD_LOGIC:='0'signal clk1:STD_LOGIC:='0'beginprocess(clk)begin if clk'event and clk='1' then if fcount1k= 24000 thenfcount1k<=1;clk1k<=not clk1k;elsefcount1k<=fcount1k +1;end if;end if;end process;clkout1k <= clk1k ;process(clk1k)begin if clk1k'event and clk1k='1' then if fcount1= 500 thenfcount1<=1;clk1<=not clk1;elsefcount1<=fcount1 +1;end if;end if;end process;clkout1 <= clk1 ;end Behavioral;2.门控电路entity gatecontrol isPort ( gatein : in STD_LOGIC; gateout : out STD_LOGIC; latch : out STD_LOGIC; reset : out STD_LOGIC);end gatecontrol;architecture Behavioral of gatecontrol issignal A:STD_LOGIC:='0'signal B:STD_LOGIC:='0'signal C:STD_LOGIC:='0'beginprocess(gatein)beginif gatein'event and gatein='1' then A<=not A;end if;if gatein'event and gatein='0' thenB<=not A;end if;end process;process(gatein,A,B)beginif gatein='0' and A='0' and B='1' thenC<='1'else C<='0'end if;end process;gateout<=A;latch<=B;reset<=C;end Behavioral;3计数器单级计数器entity counter is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; carry_in : in STD_LOGIC; carry_out : out STD_LOGIC; count_out : out STD_LOGIC_VECTOR (3 downto 0);end counter;architecture Behavioral of counter issignal count:STD_LOGIC_VECTOR (3 downto 0):="0000"beginprocess (clk,carry_in)begin if reset='1' thencount<="0000"elsif clk'event and clk='1' and carry_in='1' then if count="1001" thencount<="0000" elsecount<=count+1; end if; end if;end process;count_out<=count;carry_out<='1' when carry_in='1' and count="1001" else '0'end Behavioral;级联后计数器entity counter6 is Port ( Csignal : in STD_LOGIC; clear : in STD_LOGIC; count_en : in STD_LOGIC; out1 : out STD_LOGIC_VECTOR (3 downto 0); out2 : out STD_LOGIC_VECTOR (3 downto 0); out3 : out STD_LOGIC_VECTOR (3 downto 0); out4 : out STD_LOGIC_VECTOR (3 downto 0); out5 : out STD_LOGIC_VECTOR (3 downto 0); out6 : out STD_LOGIC_VECTOR (3 downto 0); over : out STD_LOGIC);end counter6;architecture counter6_arch of counter6 iscomponent counterport(clk : in STD_LOGIC; reset : in STD_LOGIC; carry_in : in STD_LOGIC; carry_out : out STD_LOGIC; count_out : out STD_LOGIC_VECTOR (3 downto 0);end component;signal overflow1:STD_LOGIC :='0'signal overflow2:STD_LOGIC :='0'signal overflow3:STD_LOGIC :='0'signal overflow4:STD_LOGIC :='0'signal overflow5:STD_LOGIC :='0'signal overflow6:STD_LOGIC :='0'beginu1:counter port map (Csignal,clear,count_en,overflow1,out1);u2:counter port map (Csignal,clear,overflow1,overflow2,out2);u3:counter port map (Csignal,clear,overflow2,overflow3,out3);u4:counter port map (Csignal,clear,overflow3,overflow4,out4);u5:counter port map (Csignal,clear,overflow4,overflow5,out5);u6:counter port map (Csignal,clear,overflow5,overflow6,out6);over<=overflow6;end counter6_arch;4.锁存器entity latch is Port ( data_in1 : in STD_LOGIC_VECTOR (3 downto 0); data_in2 : in STD_LOGIC_VECTOR (3 downto 0); data_in3 : in STD_LOGIC_VECTOR (3 downto 0); data_in4 : in STD_LOGIC_VECTOR (3 downto 0); data_in5 : in STD_LOGIC_VECTOR (3 downto 0); data_in6 : in STD_LOGIC_VECTOR (3 downto 0); latch_in : in STD_LOGIC; over_in : in STD_LOGIC; over_out : out STD_LOGIC; data_out1 : out STD_LOGIC_VECTOR (3 downto 0); data_out2 : out STD_LOGIC_VECTOR (3 downto 0); data_out3 : out STD_LOGIC_VECTOR (3 downto 0); data_out4 : out STD_LOGIC_VECTOR (3 downto 0); data_out5 : out STD_LOGIC_VECTOR (3 downto 0); data_out6 : out STD_LOGIC_VECTOR (3 downto 0);end latch;architecture Behavioral of latch isbeginprocess(latch_in)beginif latch_in'event and latch_in='1' thendata_out1<=data_in1;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thendata_out2<=data_in2;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thendata_out3<=data_in3;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thendata_out4<=data_in4;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thendata_out5<=data_in5;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thendata_out6<=data_in6;end if;end process;process(latch_in)beginif latch_in'event and latch_in='1' thenover_out<=over_in;end if;end process;end Behavioral;5.扫描显示控制电路entity display is Port ( value0 : in STD_LOGIC_VECTOR (3 downto 0); value1 : in STD_LOGIC_VECTOR (3 downto 0); value2 : in STD_LOGIC_VECTOR (3 downto 0); value3 : in STD_LOGIC_VECTOR (3 downto 0); value4 : in STD_LOGIC_VECTOR (3 downto 0); value5 : in STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (6 downto 0); clk1k : in STD_LOGIC; point : out STD_LOGIC; g:out STD_LOGIC; sel : out STD_LOGIC_VECTOR (2 downto 0);end display;architecture Behavioral of display issignal count:STD_LOGIC_VECTOR (2 downto 0):="000"signal dataout:STD_LOGIC_VECTOR (3 downto 0):="0000"signal hide:STD_LOGIC:='0'signal hide_4:STD_LOGIC:='0'signal hide_5:STD_LOGIC:='0'beginprocess(clk1k)beginif clk1k'event and clk1k='1' then if count="101" thencount<="000" elsecount<=count+1; end if; end if;end process;sel<=count;g<='0'process(count,value0,value1,value2,value3,value4,value5)begincase count iswhen "000" => dataout<=value0;when "001" => dataout<=value1;when "010" => dataout<=value2;when "011" => dataout<=value3;when "100" => dataout<=value4;when "101" => dataout<=value5;when others => dataout<="0000"end case;end process;process(hide,dataout)beginled<=""if hide='0' then case dataout is when "0000"=>led<=""when "0001"=>led<=""when "0010"=>led<=""when "0011"=>led<=""when "0100"=>led<=""when "0101"=>led<=""when "0110"=>led<=""when "0111"=>led<=""when "1000"=>led<=""when "1001"=>led<=""when others=>led<="" end case;end if;end process;process(count)beginif count="011" thenpoint<='0'else point<='1'end if;end process;process(value4,value5)beginif value5 = "0000"thenhide_5 <= '1' ;else hide_5 <='0'end if;if value4 = "0000" and value5 = "0000" then hide_4 <= '1'else hide_4 <='0'end if;end process;process(count)begincase count is when "000" => hide <= '0' when "001" => hide <= '0' when "010" => hide <= '0' when "011" => hide <= '0' when "100" => hide <= hide_4; when "101" => hide <= hide_5; when others => hide <='1'end case;end process;end Behavioral;6.顶层电路entity digitalfrequency is Port ( digitalsignal : in STD_LOGIC; clk24m : in STD_LOGIC; ledout : out STD_LOGIC_VECTOR (6 downto 0); sel : out STD_LOGIC_VECTOR (2 downto 0):="000" overflow : out STD_LOGIC; g : out STD_LOGIC; point: out STD_LOGIC);end digitalfrequency;architecture digitalfrequency_arch of digitalfrequency iscomponent fenpinPort ( clk : in STD_LOGIC; clkout1 : out STD_LOGIC; clkout1k : out STD_LOGIC);end component;component gatecontrolPort ( gatein : in STD_LOGIC; gateout : out STD_LOGIC; latch : out STD_LOGIC; reset : out STD_LOGIC);end component;component counter6Port ( Csignal : in STD_LOGIC; clear : in STD_LOGIC; count_en : in STD_LOGIC; out1 : out STD_LOGIC_VECTOR (3 downto 0); out2 : out STD_LOGIC_VECTOR (3 downto 0); out3 : out STD_LOGIC_VECTOR (3 downto 0); out4 : out STD_LOGIC_VECTOR (3 downto 0); out5 : out STD_LOGIC_VECTOR (3 downto 0); out6 : out STD_LOGIC_VECTOR (3 downto 0); over : out STD_LOGIC);end component;component latch Port ( data_in1 : in STD_LOGIC_VECTOR (3 downto 0); data_in2 : in STD_LOGIC_VECTOR (3 downto 0); data_in3 : in STD_LOGIC_VECTOR (3 downto 0); data_in4 : in STD_LOGIC_VECTOR (3 downto 0); data_in5 : in STD_LOGIC_VECTOR (3 downto 0); data_in6 : in STD_LOGIC_VECTOR (3 downto 0); latch_in : in STD_LOGIC; over_in : in STD_LOGIC; over_out : out STD_LOGIC; data_out1 : out STD_LOGIC_VECTOR (3 downto 0); data_out2 : out STD_LOGIC_VECTOR (3 downto 0); data_out3 : out STD_LOGIC_VECTOR (3 downto 0); data_out4 : out STD_LOGIC_VECTOR (3 downto 0); data_out5 : out STD_LOGIC_VECTOR (3 downto 0); data_out6 : out STD_LOGIC_VECTOR (3 downto 0);end component;component displayPort ( value0 : in STD_LOGIC_VECTOR (3 downto 0); value1 : in STD_LOGIC_VECTOR (3 downto 0); value2 : in STD_LOGIC_VECTOR (3 downto 0); value3 : in STD_LOGIC_VECTOR (3 downto 0); value4 : in STD_LOGIC_VECTOR (3 downto 0); value5 : in STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (6 downto 0); clk1k : in STD_LOGIC; point : out STD_LOGIC; g:out STD_LOGIC; sel : out STD_LOGIC_VECTOR (2 downto 0);end component;signal clk1k:STD_LOGIC:='0'signal clk1:STD_LOGIC:='0'signal A:STD_LOGIC:='0'signal B:STD_LOGIC:='0'signal C:STD_LOGIC:='0'signal counterout1: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterout2: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterout3: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterout4: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterout5: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterout6: STD_LOGIC_VECTOR (3 downto 0):="0000"signal counterover: STD_LOGIC;signal latchdata1: STD_LOGIC_VECTOR (3 downto 0):="0000"signal latchdata2: STD_LOGIC_VECTOR (3 downto 0):="0000"signal latchdata3: STD_LOGIC_VECTOR (3 downto 0):="0000"signal latchdata4: STD_LOGIC_VECTOR (3 downto 0):="0000"signal latchdata5: STD_LOGIC_VECTOR (3 downto 0):="0000"