VHDL4位计数器的设计.doc
*bcd译码器*library ieee;use ieee.std_logic_1164.all;entity decoder isport(bcd: in std_logic_vector(3 downto 0);y: out std_logic_vector(7 downto 0);end entity;architecture rtl of decoder isbeginprocess (bcd)begincase bcd iswhen "0000" => y<="11000000" -0: h g f e d c b awhen "0001" => y<="11111001" -1when "0010" => y<="10100100" -2when "0011" => y<="10110000" -3when "0100" => y<="10011001" -4when "0101" => y<="10010010" -5when "0110" => y<="10000010" -6when "0111" => y<="11111000" -7when "1000" => y<="10000000" -8when "1001" => y<="10010000" -9when others => y<="11111111"end case;end process;end rtl;*多路选择控制*library ieee;use ieee.std_logic_1164.all;entity mux isport (input_a:in std_logic_vector(3 downto 0);input_b:in std_logic_vector(3 downto 0);input_c:in std_logic_vector(3 downto 0);input_d:in std_logic_vector(3 downto 0);sel:in std_logic_vector(1 downto 0);y:out std_logic_vector(3 downto 0);end entity mux;architecture rtl of mux isbeginprocess(sel)isbeginif(sel="00")theny<=input_a;elsif(sel="01")theny<=input_b;elsif(sel="10")theny<=input_c;elsey<=input_d;end if;end process;end rtl;*分频*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clk4ms isport (clk:in std_logic;y:buffer std_logic);end entity clk4ms ;architecture rtl of clk4ms issignal a:STD_LOGIC_VECTOR(17 DOWNTO 0);beginprocess(clk)isbeginif(clk'event and clk='1')thenif(a="100000") thena<="0000000"y<=not y;elsea<=a+'1'end if;end if;end process;end rtl;*计数器*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt isport (clk,clr,en:in std_logic;a:out std_logic_vector(3 downto 0);b:out std_logic_vector(3 downto 0);c:out std_logic_vector(3 downto 0);d:out std_logic_vector(3 downto 0);end entity cnt ;architecture rtl of cnt issignal dout_0,dout_10,dout_100,dout_1000:std_logic_vector(3 downto 0);beginprocess(clr,clk,en)isbegina<=dout_0;b<=dout_10;c<=dout_100;d<=dout_1000;if clr='1' thendout_0<="0000"dout_10<="0000"dout_100<="0000"dout_1000<="0000"elsif(en='1')thenif(clk'event and clk='1')thenif(dout_0="1001")then -计数dout_0<="0000"elsedout_0<=dout_0+'1'end if;elsif(clk'event and clk='1' and dout_0="1001")thenif(dout_10="1001") then -计数dout_10<="0000"elsedout_10<=dout_10+'1'end if;elsif(clk'event and clk='1' and dout_0="1001" and dout_10="1001")thenif(dout_100="1001") then -计数dout_100<="0000"elsedout_100<=dout_100+'1'end if;elsif(clk'event and clk='1' and dout_0="1001" and dout_10="1001" and dout_100="1001")thenif(dout_1000="1001") then -计数dout_1000<="0000"elsedout_1000<=dout_1000+'1'end if;end if;end if;end process;end rtl;*位选*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY wei ISPORT(clk4ms:IN STD_LOGIC;q:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);d:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY wei;ARCHITECTURE rtl OF wei ISBEGINPROCESS(clk4ms) ISBEGINIF(clk4ms 'EVENT AND clk4ms='1') THENIF(q="11") THENq<="00"ELSEq<=q+'1'END IF;IF(q="00") THENd<="1000"ELSIF(q="01") THENd<="0100"ELSIF(q="10") THENd<="0010"ELSEd<="0001"END IF;END IF;END PROCESS;END ARCHITECTURE rtl;*总程序*LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY ZONG ISPORT(clr:IN STD_LOGIC;clk:IN STD_LOGIC;CLK4M:IN STD_LOGIC;en:IN STD_LOGIC;DIG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ZONG ;ARCHITECTURE a OF ZONG ISCOMPONENT cnt isport (clk,clr,en:in std_logic;a:out std_logic_vector(3 downto 0);b:out std_logic_vector(3 downto 0);c:out std_logic_vector(3 downto 0);d:out std_logic_vector(3 downto 0);END COMPONENT;COMPONENT MUX isport (input_a:in std_logic_vector(3 downto 0);input_b:in std_logic_vector(3 downto 0);input_c:in std_logic_vector(3 downto 0);input_d:in std_logic_vector(3 downto 0);sel:in std_logic_vector(1 downto 0);y:out std_logic_vector(3 downto 0);end COMPONENT;COMPONENT DECODER isport(bcd:in std_logic_vector(3 downto 0);y: out std_logic_vector(7 downto 0);end COMPONENT;COMPONENT WEI isport(clk4ms:in std_logic;q:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);d:out std_logic_vector(3 downto 0);end COMPONENT;COMPONENT CLK4MS isport(clk:in std_logic;y:out std_logic);end COMPONENT;SIGNALaa,bb,cc,dd:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL mm:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ss:STD_LOGIC;signal ww:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINu1 : cnt PORT MAP(clk,clr,en,aa,bb,cc,dd);u2 : mux PORT MAP(aa,bb,cc,dd,ww,mm);u3 :decoder PORT MAP(mm,y);u4 : wei PORT MAP(ss,ww,dig);u5 : clk4ms PORT MAP(clk4m,ss);END a;第 10 页
