ALU模块设计文档.doc
版本信息版本日期描述作者1.020/03/2015ALU模块设计文档有耀封面版本信息必须与本页最后版本保持一致。ALU模块设计方案算术逻辑运算器ALU是数字计算机中执行加、减等算术运算，执行与、或等逻辑运算，以与执行比拟、移位、传送等操作的功能部件，本模块实现32位的ALU。本文描述MIPS单周期处理器的ALU模块的功能、接口、时序与其实现。1 功能ALU主要完成：l 有符号数的加减运算l 无符号数的加减运算l 与、或逻辑运算l 算术右移l 逻辑左移、右移l 有符号小于置1运算l 无符号小于置1运算2 接口说明表1 ALU接口信号定义信号名称方向含义ALU_DA31:0INALU第一个输入数据端口，32位宽度ALU_DB31:0INALU第二个输入数据端口，32位宽度ALU_CLT3:0INALU运算功能编码，12种指令需要4位编码ALU_SHIFT4:0IN ALU移位次数ALU_ZEROOUT运算结果全零标志ALU_OverFlowOUT有符号运算溢出标志ALU_DC31:0OUTALU运算结果3 时序说明ClkPCRs, Rt, Rd,Op, FuncClk-to-QALUctrInstruction Memory Access TimeOld ValueNew ValueRegWrOld ValueNew ValueDelay through Control LogicbusARegister File Access TimeOld ValueNew ValuebusBALU DelayOld ValueNew ValueOld ValueNew ValueNew ValueOld ValueExtOpOld ValueNew ValueALUSrcOld ValueNew ValueMemtoRegOld ValueNew ValueAddressOld ValueNew ValuebusWOld ValueNewDelay through Extender & MuxRegisterWrite OccursData Memory Access TimePC+4PC+4 PC 4 实现方案算术逻辑运算器ALU的具体实现方案如图1。分析图1的功能，并按功能要求将图1补充完整即与逻辑和移位功能的实现。图1 ALU实现方案表1 ALU控制信号SUBctr = ALUctr<2>作为加减控制信号，同时作为与或控制信号ANDctr = ALUctr<0>OVctr = !ALUctr<1>&ALUctr<0>SIGctr = ALUctr<0>OPctr<1> = ALUctr<2> & ALUctr<1>OPctr<0> = !ALUctr<2> & ALUctr<1> & !ALUctr<0>| ALUctr<3>根据Opctr=2b11时作为移位输出选择、ALUctr<3:0>=4b10000逻辑左移，ALUctr<3:0>=4b10001逻辑右移，ALUctr<3:0>=4b10010算术右移等要求修改补充表1。5 电路设计描述module (ALU_DA,ALU_DB,ALU_CLT,ALU_SHIFT,ALU_ZERO,ALU_OverFlow,ALU_DC)input 31:0 ALU_DA;input 31:0 ALU_DB;input 3:0 ALU_CLT;input 4:0 ALU_SHIFT;output ALU_ZERO;output ALU_OverFlow;output 31:0 ALU_DC;reg 31:0 ALU_DC;wire 1:0 OPctr;wire SUBctr;wire ANDctr;wire OVctr;wire SIGctr;reg 31:0 SLL_M,SRL_M,SRA_M;assign SUBctr = ALUctr2;assign ANDctr = ALUctr0;assign OVctr = !ALUctr1&ALUctr0;assign SIGctr = ALUctr0;assign OPctr<1> =ALUctr2 & ALUctr1;assign OPctr<0> = ?!ALUctr2 & ALUctr1 & !ALUctr0?| ALUctr3;always /SRLbegin case(ALU_SHIFT) 5'b00000:SRL_M31:0=ALU_DA31:0; 5'b00001:SRL_M31:0=1'b0,ALU_DA31:1; 5'b00010:SRL_M31:0=2'b0,ALU_DA31:2; /. 5'b11111:SRL_M31:0=31'b0,ALU_DA31; default: SRL_M31:0=ALU_DA31:0; endcaseendalways /SLLbegin case(ALU_SHIFT) 5'b00000:SLL_M31:0=ALU_DA31:0; 5'b00001:SLL_M31:0=ALU_DA30:0,1'b0; 5'b00010:SLL_M31:0=ALU_DA29:0,2'b0; /. 5'b11111:SLL_M31:0=ALU_DA0,31'b0; default: SLL_M31:0=ALU_DA31:0; endcaseendalways /SRAbegin case(ALU_SHIFT) 5'b00000:SRA_M31:0=ALU_DA31:0; 5'b00001:SRA_M31:0=1ALU_DA31,ALU_DA31:1; 5'b00010:SRA_M31:0=2ALU_DA31,ALU_DA31:2; /. 5'b11111:SRA_M31:0=31ALU_DA31,ALU_DA31; default: SRA_M31:0=ALU_DA31:0; endcaseendreg 31:0 Soutput;wire 1:0 Sctr;assign Sctr=ALU_CTL1:0;always /SHIFTbegin case(Sctr) 2'b00:Soutput=SRL_M; 2'b01:Soutput=SLL_M; 2'b10:Soutput=SRA_M; default: Soutput=ALU_DA; endcaseend/AND OR logicwire 31:0 OR_M,AND_M,AND_OR_output;assign OR_M=ALU_DA | ALU_DB;assign AND_M=ALU_DA & ALU_DB;assign AND_OR_output=(ANDctr=1'b1)?AND_M:OR_M;/ADDERwire 31:0 BIT_M,XOR_M;assign BIT_M=32SUBctr;assign XOR_M=BIT_MALU_DB;wire ADD_carry,ADD_OverFlow;wire 31:0 ADD_result;assign ADD_carry,ADD_result=ALU_DA+XOR_M+SUBctr;assign ALU_ZERO=(|ADD_result);assign ADD_OverFlow=(ALU_CTL=4'b0001)&&(ALU_DA31=0)&&(ALU_DB31=0)&&(ADD_result31=1)|(ALU_CTL=4'b0001)&&(ALU_DA31=1)&&(ALU_DB31=1)&&(ADD_result31=0) |(ALU_CTL=4'b0101)&&(ALU_DA31=1)&&(ALU_DB31=0)&&(ADD_result31=0)|(ALU_CTL=4'b0101)&&(ALU_DA31=0)&&(ALU_DB31=1)&&(ADD_result31=1);assign ALU_OverFlow=ADD_OverFlow & OVctr;/SLTwire LESS_M1,LESS_M2,LESS_S,SLT_M;assign LESS_M1=ADD_carry SUBctr;assign LESS_M2= ADD_OverFlow ADD_result31;assign LESS_S= (SIGctr=1'b0):LESS_M1:LESS_M2;assign SLT_M= (LESS_S=1'b1):32'hffffffff:32'h00000000;/RESULTalways begin case(OPctr) 2'b00:ALU_DC=ADD_result; 2'b01:ALU_DC=AND_OR_output; 2'b10:ALU_DC=SLT_M; 2'b11:ALU_DC=Soutput; endcaseendendmodule5 仿真验证ALU_DA31:0、ALU_DB31:0是两个输入运算数据，ALU_DC31:0为运算结果，ALU_ZERO为运算结果的全零标志，ALU_OverFlow为算术运算异常标志，ALU_SHIFT4:0为移位次数输入，ALU_CLT3:0为ALU操作控制信号。ALU_CTL取值可为0、1、2、3、4、5、6、7、8、9、10分别对应无符号加、有符号加、逻辑或、逻辑与、无符号减、有符号减、无符号小于置1、有符号小于置1、逻辑右移、逻辑左移、算术右移。通过设置两个输入数据、移位次数信号，然后改变控制输入信号，查看输出结果是否正确。7 / 7
