指导教授林志明.ppt
An Ultra-Low-Power,TemperatureCompensated Voltage Reference Generator指導教授:林志明 教授學 生:劉彥均IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCEOutlinenCircuit DescriptionnSupply Voltage DynamicnTemperature CompensationnLine SensitivitynExperimental ResultsnConclusionCircuit DescriptionCircuit DescriptionnA low temperature drift voltage reference is obtained by compensating the temperature dependence of the generated current with the temperature dependence of the NMOS threshold voltage.nThe particular configuration used allows us to suppress the effect of the temperature dependence of mobility.The proposed voltage reference was implemented in AMS 0.35 m CMOS IC technology.Circuit Description(A)Current Generator Circuit(1)nIn order to reduce the channel modulation effect that causes a mismatch between the currents in the two branches,the channel lengths of the two transistors M5 and M6 are chosen large enough.Circuit Description(A)Current Generator Circuit(2)nTransistors M1 and M2 are biased in the subthreshold region,while transistors M3 and M4 work in the saturation region.region.Such behavior is achieved through careful biasing:The gate-source voltage of M3(M4)must be larger than the gate-source voltage of M1(M2)nSince the four transistors have the same drain current The W/L ratio of M1(M2)has to be larger than that of M3(M4).Circuit Description(A)Current Generator Circuit(3)nThe I-V characteristics of a MOS transistor that operates in the saturation and in the subthreshold region can be approximated by(1)and(2),respectively.Circuit Description(A)Current Generator Circuit(4)nAssuming that the currents in the two branches of the current circuit generator are equal,the current becomes:Circuit Description(A)Current Generator Circuit(5)nThe effect of channel length modulation of M1 and M2 is negligible(subthreshold region,).nThe channel length modulation effect of M3 and M4 is negligible since they are long-channel devices,and since their drain-source voltages have very small variations,when the supply voltage is varied.Circuit Description(A)Current Generator Circuit(6)nAlmost all the variation of the supply voltage drops 1)on the drain-source voltage of M2,without causing large variations of the current I0,since it works in the subthreshold region,2)on the drain-source voltage of M5.Circuit Description(B)Active Load(1)nThe active load used to generate a reference voltage with a low temperature drift.nThe output voltage reference has the expression:nIn order to ensure the correct temperature compensation it is necessary that most of the bias current flows through the transistor M7 and M8 rather than through the resistances R1 and R2.Circuit Description(B)Active Load(2)nWe determine the minimum value of the bias current that ensures the correct operation of the voltage reference generatorSupply Voltage Dynamic(1)nWe have to ensure that the transistor M2 has a drain-source voltage of at least 100 mV so that the effect of the drain-source voltage in(2)and then the channel length modulation of M2 can be neglected.Consequently,the following expression has to be satisfiedSupply Voltage Dynamic(2)nThe maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors,as shown belowTemperature Compensation(1)nThe threshold voltage of an NMOS transistor decreases linearly with the temperature,as shown below where is a BSIM3v3 coefficient that models the temperature dependence of the threshold voltage.BSIM3(Berkeley Short channel Insulated gate field effect transistor Model)模型是由加州柏克萊分校(UC Berkeley)在1993 發表的重要技 術，而此元件模型可用模擬含括0.18m(0.110-6 m)MOS 元件的 比電與位電Temperature Compensation(3)nLet us define h asnFrom(3),(4)and(9),and assuming that(5)is fulfilled,we can derive the following expression for the reference voltageTemperature Compensation(4)nDifferentiating(10)with respect to the temperature and taking into account(8),one obtains where is the Boltzmann constant and q is the electron chargeTemperature Compensation(5)nEquating(11)to zero,we obtainLine SensitivitynBy calculating and from(1)and substituting them in(4),we can derive the following expression for the output voltageExperimental Results(1)n mean reference voltage of about 168 mV with a variation of 2.3 mV at room temperature when the supply voltage varies from 1.5 V to 4.3 VnThe measured temperature coefficient at VDD=2 V and VDD=3 V is 25 ppm/C and increases to 37 and 39 ppm/C at VDD=4.3 V and VDD=1.5 V.nAt 80 C the current drawn at the maximum supply voltage is 2.4 A and at the minimum supply voltage is 1.5 A.Experimental Results(2)Experimental Results(3)Experimental Results(4)nThe power supply rejection ratio,without any filtering capacitor,is-65 dB at 100 Hz and-57 dB at 10 MHz,for the smallest supply voltage.Experimental Results(5)ConclusionnA 25 ppm/C voltage reference with a supply current of only 1.2 A,at 1.5 V,has been presented.nThe proposed voltage reference has been implemented with a standard 0.35 CMOS process.nParticular attention has been put at minimizing the power consumption,achieving at the same time very good PSRR and temperature compensation,without any trimming procedure.
