原版的操作系统_精髓与设计原理_第5版chapter01.pdf

Computer System OverviewChapter 1Chapter 11Operating SystemOperating SystemEl ih h df Exploits the hardware resources of one or more processors Provides a set of services to system usersMdd I/O Manages secondary memory and I/O devices2Basic ElementsBasic Elements Processor Processor Main Memory volatilevolatile referred to as real memory or primary memory I/O modulesI/O modules secondary memory devices communications equipmentq p terminals System bus communication among processors,memory,and I/O modules3ProcessorProcessorTili Two internal registers Memory address register(MAR)Specifies the address for the next read or write Memory buffer register(MBR)Memory buffer register(MBR)Contains data written into memory or receives data read from memory y I/O address registerI/O buffer register I/O buffer register4Top Level ComponentsTop-Level ComponentsCPUMain MemoryPCMARIRMBRySystemBusInstruction012InstructionInstructionIRMBRI/O ARI/O BRDataDataDataExecutionunitI/O Modulen-2n-1DataBuffersPC=Program counterIR=Instruction registerMAR=Memory address registerFigure 1.1 Computer Components:Top-Level ViewMAR Memory address registerMBR=Memory buffer registerI/O AR=Input/output address registerI/O BR=Input/output buffer register5gu e.Copu e Copo es:opeve V ewProcessor RegistersProcessor RegistersUi ibli t User-visible registers Enable programmer to minimize main-fbti i ii tmemory references by optimizing register useCldi Control and status registers Used by processor to control operating of the processor Used by privileged operating-system routines to control the execution of programs6User Visible RegistersUser-Visible RegistersMbfd bhil May be referenced by machine language Available to all programs-application programs and system programs Types of registersypes oeg s e s Data Address Address Index Segment pointerSegment pointer Stack pointer7User Visible RegistersUser-Visible RegistersAddRi Address Registers Index Involves adding an index to a base value to get an address Segment pointer When memory is divided into segments,yg,memory is referenced by a segment and an offset Stack pointer Points to top of stack8pControl and Status RegistersControl and Status RegistersPCt(PC)Program Counter(PC)Contains the address of an instruction to be fetched Instruction Register(IR)Contains the instruction most recently fetched Program Status Word(PSW)Condition codes Interrupt enable/disable Supervisor/user modeSupervisor/user mode9Control and Status RegistersControl and Status RegistersCdi iC dFl Condition Codes or Flags Bits set by the processor hardware as a result of operations Examplesp es Positive result Negative resultNegative result Zero OverflowOverflow10Instruction ExecutionInstruction ExecutionT Two steps Processor reads instructions from memory Fetches Processor executes each instructionProcessor executes each instruction11Instruction CycleInstruction Cycle12Instruction Fetch and ExecuteInstruction Fetch and ExecuteThfhh ii The processor fetches the instruction from memory Program counter(PC)holds address of the instruction to be fetched nextthe instruction to be fetched next Program counter is incremented after each fetch13Instruction RegisterInstruction Register Fetched instruction is placed in the instruction Fetched instruction is placed in the instruction register Categories Categories Processor-memory Transfer data between processor and memory Transfer data between processor and memory Processor-I/O Data transferred to or from a peripheral device Data processing Arithmetic or logic operation on datal Control Alter sequence of execution14Characteristics of a Hypothetical Machine15Example of Program ExecutionExample of Program Execution16Direct Memory Access(DMA)I/Ohdili h I/O exchanges occur directly with memory Processor grants I/O module authority to read from or write to memoryread from or write to memory Relieves the processor responsibility for the exchange17InterruptsInterruptsIhlif h Interrupt the normal sequencing of the processor Most I/O devices are slower than the processorprocessor Processor must pause to wait for device18Classes of InterruptsClasses of Interrupts19Program Flow of Control Without Interrupts20Program Flow of Control With Interrupts,Short I/O WaitUserI/OProgramProgramI/OCommand14WRITECommand2aWRITEInterruptHandler2b5END3aWRITE3b(b)Interrupts;short I/O wait21(b)Interrupts;short I/O waitProgram Flow of Control With Interrupts;Long I/O Wait22Interrupt HandlerInterrupt HandlerPiilI/O Program to service a particular I/O device Generally part of the operating system23InterruptsInterruptsSdhlf Suspends the normal sequence of execution24Interrupt CycleInterrupt Cycle25Interrupt CycleInterrupt CyclePhk fi Processor checks for interrupts If no interrupts fetch the next instruction pfor the current programIfi tt idid If an interrupt is pending,suspend execution of the current program,and execute the interrupt-handler routine26Timing Diagram Based on Short I/O Wait27Timing Diagram Based on Short I/O Wait28Simple Interrupt ProcessingSimple Interrupt Processing29Changes in Memory and Registers for an Interrupt30Changes in Memory and Registers for an Interrupt31Multiple InterruptsMultiple InterruptsDibl i tthili tt i Disable interrupts while an interrupt is being processed32Multiple InterruptsMultiple InterruptsD fiiitifi tt Define priorities for interrupts33Multiple InterruptsMultiple Interrupts34MultiprogrammingMultiprogrammingPhtht Processor has more than one program to execute The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O After an interrupt handler completes,After an interrupt handler completes,control may not return to the program that was executing at the time of thethat was executing at the time of the interrupt35Memory HierarchyMemory HierarchyFibi Faster access time,greater cost per bit Greater capacity,smaller cost per bitpy,p Greater capacity,slower access speed36Memory HierarchyMemory Hierarchy37Going Down the HierarchyGoing Down the HierarchyDibi Decreasing cost per bit Increasing capacitygpy Increasing access time Decreasing frequency of access of the memory by the processory yp Locality of reference38Secondary MemorySecondary MemoryNl il Nonvolatile Auxiliary memoryyy Used to store program and data files39Disk CacheDisk CacheAifid A portion of main memory used as a buffer to temporarily to hold data for the disk Disk writes are clustered Disk writes are clustered Some data written out may be referenced again.The data are retrieved rapidly from the software cache instead of slowly from disk40Cache MemoryCache MemoryIi ibli Invisible to operating system Increase the speed of memorypy Processor speed is faster than memory dspeed Exploit the principle of localitypppy41Cache MemoryCache Memory42Cache MemoryCache MemoryCififi Contains a copy of a portion of main memory Processor first checks cacheIft fd ihth blk f If not found in cache,the block of memory containing the needed information is moved to the cache and delivered to the processorp43Cache/Main Memory SystemCache/Main Memory SystemMemoryLineaddress0120123Block(K words)NumberTagBlockC-1Block Length(K Wd)(K Words)(a)CachenBlock2n-1WordLength(b)Main memoryFigure 1.17 Cache/Main-Memory StructureFigure 1.17 Cache/Main Memory StructureCache Read OperationCache Read Operation45Cache DesignCache DesignChi Cache size Small caches have a significant impact on performanceperformance Block size The unit of data exchanged between cache and main memoryLblk ihiilb bilif Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to beprobability of reusing data that have to be moved out of cache46Cache DesignCache DesignMifi Mapping function Determines which cache location the block will occupy Replacement algorithmReplacement algorithm Determines which block to replaceld()li h Least-Recently-Used(LRU)algorithm47Cache DesignCache DesignW ili Write policy When the memory write operation takes place Can occur every time block is updatedCoccu eve ye b ocs upd ed Can occur only when block is replaced Minimizes memory write operations Minimizes memory write operations Leaves main memory in an obsolete state48Programmed I/OProgrammed I/OI/Od lfth I/O module performs the action,not the processor Sets appropriate bits in the I/O status register No interrupts occur Processor checks status untilProcessor checks status until operation is complete49Interrupt Driven I/OInterrupt-Driven I/OPi i tt dhI/O Processor is interrupted when I/O module ready to exchange data Processor saves context of Processor saves context of program executing and begins executing interrupt-handlergp No needless waiting Consumes a lot of processor time pbecause every word read or written passes through the processor50Direct Memory AccessDirect Memory AccessTfblk f d t Transfers a block of data directly to or from memory An interrupt is sent when the transfer is complete Processor continues with other work51