逻辑综合与时序仿真课件.ppt

Unit 4 VLSI设计方法设计方法Chap10 逻辑综合与时序仿真逻辑综合与时序仿真Unit 1 绪论绪论Unit 2 CMOS电路设计基础电路设计基础Unit 3 CMOS电路的逻辑设计电路的逻辑设计Unit 4 VLSI设计方法设计方法 Chap8 设计模式和设计流程设计模式和设计流程 Chap9 RTL设计与仿真设计与仿真 Chap10 逻辑综合与时序仿真逻辑综合与时序仿真 Chap11 可测试性设计与可测试性设计与ATPG Chap12 版图设计与验证版图设计与验证SpecificationExecutable modelRTL code Gate-level netlistCell/interconnect level positionMask-level geometrySystem(Behavioral)levelRTL Gate(Logic)levelLayout (Physical)Level设计阶段设计阶段（设计抽象层）（设计抽象层）设计结果设计结果Logic Design&Simulation:from RTL,then in Gate-LevelLogic Synthesis l得到得到用已有的基本逻辑单元（库单元）互联并满足一定逻辑用已有的基本逻辑单元（库单元）互联并满足一定逻辑功能的逻辑构成功能的逻辑构成Gate-Level Simulation（门级功能仿真与动态时序门级功能仿真与动态时序分析）分析）l一般不做这一步一般不做这一步Formal Verification（形式验证）（形式验证）STA（Static Timing Analysis，静态时序分析）静态时序分析）HDL Coding for SynthesisBased on Synopsys Design CompilerThe Importance of Quality of Source Code Codes that are functionally equivalent,but coded differently will give different synthesis results.You cannot rely solely on Design Compiler to“fix”a poorly coded design!Try to understand the“hardware”you are describing,to give DC the best possible starting point.Think Hardware!Write HDL hardware descriptions l Think of the topology implied by the code Do not write HDL simulation models l No explicit delays l No file I/O Think Synchronous!Synchronous designs run smoothly through synthesis,simulation,test,and layout Asynchronous designs may require hand instantiation and extensive simulation to verify l Isolate asynchronous logic into separately compiled blocks Think RTL!Writing in an RTL coding style means describing:lthe circuit topologylthe register placementlthe functionality between registersDC optimizes logic between registers:lIt does not optimize the register placementSynthesis of if Statements(1)The if-else construct implies multiplexing hardwareActual circuit implementation depends on target library and ConstraintsSynthesis of if Statements(2)To infer latches,use an if statement without an else clauseSynthesis of case Statementsimply parallel mux functionSynthesis of Flip-FlopsSynthesis of Flip-FlopsSynthesisBased on Synopsys Design Compiler0.Introduction to Synthesis1.Pre-Synthesis Processes2.Constraining the Design3.Synthesizing the DesignWhat Is Synthesis?Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function.l在在包包含含众众多多结结构构、功功能能、性性能能均均已已知知的的逻逻辑辑单单元元电电路路的的目目标标工工艺艺库库的的支支持持下下l得得到到目目标标工工艺艺库库中中单单元元电电路路的的连连接接关关系系（逻逻辑辑网络）的最佳实现方案网络）的最佳实现方案l满满足足设设计计电电路路的的功功能能要要求求以以及及速速度度、面面积积等等限限制条件制条件Synthesis Internal Flow Synthesis Is Constraint-Driven Synthesis Is Path-Based 0.Introduction to Synthesis1.Pre-Synthesis ProcesseslTechnology Library for synthesislDesign Hierarchy and Partition2.Constraining the Design3.Synthesizing the DesignTechnology Library(1)工艺库由工艺库由Foundary提供，一般是提供，一般是.db的格式，这种格式是的格式，这种格式是DC认识的一认识的一种内部文件格式，不能由文本方式打开种内部文件格式，不能由文本方式打开.db格式可以由文本格式格式可以由文本格式.lib转化过来转化过来 Technology Library(2)During mapping,DC will:lchoose functionally-correct gates from this library lcalculate the timing of the circuit using vendor-supplied timing data for these gates target_library is a reserved variable in DC，you should set it to point to the Technology library file(s)provided by your silicon vendorDesign Hierarchy:RISC_CORE example Design Hierarchy(Partitioning)within HDL Description 编写编写HDL代码之前（系统设计阶段）都需要系统划分，代码之前（系统设计阶段）都需要系统划分，根据功能或者其他的原则将一个系统层次化地分成若干根据功能或者其他的原则将一个系统层次化地分成若干个模块，这些模块内部再进一步细分成模块个模块，这些模块内部再进一步细分成模块/子模块子模块Entity(VHDL)and module(Verilog)statements define hierarchical blocks.Inference of Arithmetic Circuits(+,-,*,.)can create a new level of hierarchy.Process(VHDL)and always(Verilog)statements do not create hierarchy Repartitioning to Design Hierarchy for Synthesis在在DC做综合的过程中，默认的情况下各个做综合的过程中，默认的情况下各个模块的层次关系是保留着的。保留着的层次模块的层次关系是保留着的。保留着的层次关系会关系会对对DC综合造成一定的影响，比如在综合造成一定的影响，比如在优化的过程中，各个模块的管脚必须保留，优化的过程中，各个模块的管脚必须保留，这势必影响到模块边界的优化效果这势必影响到模块边界的优化效果 Why Partitioning/RepartitioningPartitioning or Repartitioning is driven by many(often competing)needs:l Separate distinct functions l Achieve workable size and complexityl Manage project in team environment l Design Reuse l Meet physical constraintsl And many,many othersPoor Partitioning:so Should Eliminate Unnecessary HierarchyGood Partitioning(1):No Hierarchy in Combinational Paths Good Partitioning(2):No Hierarchy in Combinational PathsGood Partitioning(3):Partition at Register BoundariesExample(1):Avoid Glue LogicExample(2):Remove Glue Logic Between BlocksBalance Block Size in Partitioning(1)Balance Block Size in Partitioning(2)Top-Level Design PartitioningRepartitioning within Design Compiler The group and ungroup commands modify the partitions in a design.Group creates a new hierarchical block.Ungroup removes either one or all levels of hierarchy.GroupUngroup0.Introduction to Synthesis1.Pre-Synthesis Processes2.Constraining the Design lArea ConstraintslTiming Constraints and Time BudgetinglEnvironmental AttributeslClock Constraints 3.Synthesizing the DesignSpecifying Area Constraints 施加了一个最大面积施加了一个最大面积100单位的约束单位的约束Units are those of target library,defined by the vendor:l 2-input-NAND-gatel transistorsl square milsSpecify Timing Constraints(1)Synchronous Designs:l Data arrives from a clocked device l Data goes to a clocked device Objective:Define the timing constraints for all paths within a design:1.The internal(register to register)paths 2.All input paths 3.All output paths Specify Timing Constraints(2)1.Creating a clock constrains timing paths between registerscreate_clock-period 10 get_ports ClkSpecify Timing Constraints(3)2.Constraining the Input Paths set_input_delay max(input delay)clock Clk get_ports ClkSpecify Timing Constraints(4)3.Constraining Output Paths set_output_delay max(output delay)clock Clk get_ports ClkTime Budgeting(1)What if you do not know the delays on your inputs or the setup requirements of your outputs?Create a Time Budget!Time Budgeting(2)Time BudgetingTime Budgeting:Example lTime Budgeting for MY_BLOCKlTime Budgeting for X_BLOCK and Y_BLOCK Time Budgeting(3)Constraining for Timing:What Is Missing?输输入入输输出出的的电电平平转转换换时时间间(transition time)由由输输入入外外围围电电路路的的驱驱动动能力能力和和输出外围电路的负载大小输出外围电路的负载大小决定决定电路内部的电路内部的互连线时延互连线时延的估计的估计当当外界温度或者电路供电电压发生变化外界温度或者电路供电电压发生变化时，时延会相应的改变时，时延会相应的改变Environmental Attributes(1)set_driving_cell:Input Drive StrengthEnvironmental Attributes(2)set_load:Output Capacitive Load Environmental Attributes(3)set_wire_load_model:Net DelayslA Wire Load Model(WLM)is an estimate of a nets RC parasitics based on the nets fanout:l Model is created by your vendor l Estimates are based on statistics from other designs the vendor has fabricated using this processlSpecifying WLM in Design Compiler Environmental Attributes(4)Operating ConditionslWhy?Library cells are usually characterized using“nominal”voltage and temperature.If not lWhat?Vendors allow for synthesis of circuits which will not operate under“nominal”conditions by embedding other operating conditions in the technology libraries lvendor-supplied operating conditions(vendors might deliver multiple technology libraries)Operating Conditions lTo set operating conditions,enter set_operating_conditions commandlDuring synthesis,“nominal”cell and wire delays will be scaled based on the operating conditionsClock Constraints(1)Recall Timing ConstraintsClock Constraints(2)对时钟网络进行综合时，需要在时钟的各条路径上要插对时钟网络进行综合时，需要在时钟的各条路径上要插入大小不一的入大小不一的buffer，目的是为了保证时钟到达每个触，目的是为了保证时钟到达每个触发器的时延尽量相等发器的时延尽量相等在定义时钟之后，都要给该时钟设置在定义时钟之后，都要给该时钟设置dont_touch，告，告诉诉DC不要对时钟网络进行综合（插入不要对时钟网络进行综合（插入Buffer）。这是）。这是因为综合时钟网络需要考虑单元的实际物理位置，这是因为综合时钟网络需要考虑单元的实际物理位置，这是前端的逻辑综合（前端的逻辑综合（DC）不能完成的工作不能完成的工作Clock Constraints(3)Modeling Clock Skewl虽虽然然DC无无法法最最终终综综合合时时钟钟树树，但但是是可可以以加加入入一一些些约约束束让让此此时时的的时钟更加接近实际的工作情况时钟更加接近实际的工作情况l实实际际的的时时钟钟达达到到各各个个触触发发器器的的时时间间不不是是一一样样的的，它它们们之之间间的的偏偏差差称称为为时时钟钟偏偏差差(Clock Skew)。为为了了反反映映这这个个偏偏差差，我我们们在在综综合合时时可以用一个命令来模拟它可以用一个命令来模拟它Clock Constraints(4)Modeling Source Latency lClock到到达达模模块块的的端端口口后后，要要到到达达内内部部的的触触发发器器，也也要经过一定的延时，这个延时称为要经过一定的延时，这个延时称为Network Latency0.Introduction to Synthesis1.Pre-Synthesis Processes2.Constraining the Design3.Synthesizing the DesignnMultiple InstancesnHow to Compile a Hierarchical DesignnTiming Analysis and ReportMultiple Instances(1)Designs Instantiated More Than Onceuniquifycompile+dont_touchMultiple Instances(2)uniquify pile+dont_touchcompile+dont_touch由于只需对多次例化的模块编译一次，可以减少整个设计的由于只需对多次例化的模块编译一次，可以减少整个设计的编译时间，减少内存的使用量。在多次例化的模块很复杂并编译时间，减少内存的使用量。在多次例化的模块很复杂并且工作站硬件条件有限的情况下，其优越性比较明显。且工作站硬件条件有限的情况下，其优越性比较明显。如果如果这个这个Ades是一个第三方提供的是一个第三方提供的IP硬核硬核(hard-core)，那么也只那么也只能使用这种方法能使用这种方法在编译顶层模块时，由于在编译顶层模块时，由于Ades设置了设置了dont_touch，这就妨这就妨碍了碍了DC针对针对Ades的各个实例周围环境的不同的进一步优化，的各个实例周围环境的不同的进一步优化，从而使得结果不能真实反映各个实例周围的环境变化从而使得结果不能真实反映各个实例周围的环境变化Uniquify由于把各个多例化模块作为独立的模块来看，因此由于把各个多例化模块作为独立的模块来看，因此DC可以分可以分别针对它们作出更好的优化，从而得到的结果比较理想别针对它们作出更好的优化，从而得到的结果比较理想编译的时间稍微较长，但是对于一些不大的模块来说，这些编译的时间稍微较长，但是对于一些不大的模块来说，这些是可以忽略的。是可以忽略的。一般推荐使用一般推荐使用uniquify解决多例化模块的综合问题。解决多例化模块的综合问题。Compiling a Hierarchical Design(1)对一个大型设计来讲，有两种层次化编译技术对一个大型设计来讲，有两种层次化编译技术l自上而下自上而下(Top-down)l将整个设计一次性读入，施加顶层约束后直接进行编译将整个设计一次性读入，施加顶层约束后直接进行编译l无需考虑各个模块无需考虑各个模块/子模块之间的依赖关系子模块之间的依赖关系，也就不需要制模，也就不需要制模块块/子模块之间的时序预算和负载预算，都由子模块之间的时序预算和负载预算，都由DC自动考虑自动考虑l编写脚本变得简单，维护起来也比较方便编写脚本变得简单，维护起来也比较方便l自下而上自下而上(Bottom-up)l先单独编译各个模块先单独编译各个模块/子模块：在编译要考虑与其它模块之间子模块：在编译要考虑与其它模块之间的关系，给它们加入时序预算和负载预算，看是否满足约束的关系，给它们加入时序预算和负载预算，看是否满足约束l再读入顶层文件，施加顶层约束，将各个模块再读入顶层文件，施加顶层约束，将各个模块/子模块整合起子模块整合起来：顶层编译完成后还必须看顶层约束是否满足来：顶层编译完成后还必须看顶层约束是否满足Compiling a Hierarchical Design(2)Pros&Cons of Bottom-Up Compile 优点优点l利用利用”分而治之分而治之”的策略，对于大型的不可能一次编译的设计的策略，对于大型的不可能一次编译的设计十分有用十分有用l摆脱了摆脱了Top-down方法的对工作站硬件条件的限制，使得大型方法的对工作站硬件条件的限制，使得大型设计也能在一般的机器上编译完成设计也能在一般的机器上编译完成 缺点缺点l实现步骤比较多，尤其对各个模块之间的时序和负载预算要求实现步骤比较多，尤其对各个模块之间的时序和负载预算要求很高很高SummaryTiming Analysis and Report(1)What Tool to Use?lDesign Compiler has a built-in static timing analyzer called DesignTimeTiming Analysis and Report(2)DesignTime Timing ReportsLogic Design&Simulation:from RTL,then in Gate-LevelLogic Synthesis l得到得到用已有的基本逻辑单元（库单元）互联并满足一定逻辑用已有的基本逻辑单元（库单元）互联并满足一定逻辑功能的逻辑构成功能的逻辑构成Gate-Level Simulation（门级功能仿真与动态时序门级功能仿真与动态时序分析）分析）l一般不做这一步一般不做这一步Formal Verification（形式验证）（形式验证）STA（Static Timing Analysis，静态时序分析）静态时序分析）STA Based on Synopsys PrimeTimeWhat is Static Timing Analysis?Static Timing Analysis（STA）determines if a circuit meets timing constraints without dynamic simulation Three main steps:l Design is broken down into sets of timing paths l The delay of each path is calculated l All path delays are checked to see if timing constraints have been metSTA Step 1:Timing PathsStep1实际是将逻辑电路网表转换成拓扑图，实际是将逻辑电路网表转换成拓扑图，图中的节点图中的节点(node)代表电路中的引脚代表电路中的引脚(pin)，节点之间的边节点之间的边(edge)表示时序弧表示时序弧(timing arc)下图展示了逻辑电路网络转化成的拓扑图下图展示了逻辑电路网络转化成的拓扑图STA Step 2:Path Delay Calculation(1)Cell delay calculation STA Step 2:Path Delay Calculation(2)Net delay calculation STA Step 3:ConstraintsStatic Timing Analysis FlowTiming ReportFlow Step 2:Constraining DesignFlow Step 3:Specify Cell&Net Delay Info(Pre-Layout)Flow Step 4:Timing Analysis and Timing ReportTiming Report(Page 2)Timing Report(Page 3)SummaryLogic Synthesis：Constraint-Driven,Path-BasedlPre-Synthesis ProcesseslTechnology LibrarylDesign Hierarchy and Partition/RepartitionlConstraining the Design lArea ConstraintslTiming Constraints and Time BudgetinglEnvironmental AttributeslClock ConstraintslSynthesizing the DesignlResolving Multiple InstanceslHow to Compile a Hierarchical DesignlTiming Analysis and ReportSTAl原理：3 main stepslBroken into sets of timing pathslPath delay calculationlChecked if timing constraints have been metlConstraining the DesignlSpecify Cell&Net Delay InfolTiming Analysis and Timing Report