IC工艺技术9-双极型集成电路工艺技术.ppt
集成电路工艺技术讲座第九讲双极型集成电路工艺技术双极集成电路工艺技术集成电路中的晶体管和无源器件工艺和设计的界面设计手册PN隔离双极工艺流程先进双极工艺工艺和器件模拟在工艺设计中的应用（一）集成电路中的晶体管和无源器件NPN晶体管结构外延和隔离埋层和深集电极PNP晶体管集成电阻和电容集成电路中的NPN晶体管集成电路中的PNP体管集成电路中的PNP体管集成电阻pn金属集成电阻 Pinch电阻 P base衬底N Epi集成电容NP+金属介质层（二）工艺和设计的界面设计手册器件和工艺指标设计规则简要工艺流程和光刻版顺序光刻版制作要求PCM文件模型参数2um 18V specParameter SymbolMinTypMaxUnitNPN transHfe80140250Bvceo1835-VLPNP transHfe100250400Bvceo1840-VIso BVBviso2035-VField Vth Vth182536VCapacit.CAP8.510.612.7PfImplant R IR18.4k23k27.6k2um 18V specItemMinTypMaxSize(um2)R BN()10515019520 x200R-Epi()7.35k10.5k13.5k20 x200R-DN()15253520 x200R-PBAS()1.9k2.15k2.4k20 x200R-XBAS()21030039020 x200R-IR()18.4k23.0k27.6k20 x200R-NEMT()608010020 x200设计规则设计与工艺制作的接口目的：使芯片尺寸在尽可能小的前提下，避免线条宽度的偏差和不同层版套准偏差可能带来的问题，以提高电路的成品率内容：根据实际工艺水平(包括光刻特性、刻蚀能力、对准容差等)，给出的一组同一工艺层及不同工艺层之间几何尺寸的限制，主要包括线宽、间距、覆盖、露头、面积等规则，分别给出它们的最小值，2um 18V设计规则例 BPa min width 4umb clearance to BN 8umBN2.bISO IslandBP2.a2.cISO IslandDummy island Island2um 18V设计规则例 Deep N+a Min.Width 4.0umc BN extension DN 1.0umd Clearance to BP 9.0umBNDNDN3.a3.c3.b3.b3.eISO IslandBP3.d2um 18V设计规则例 Isolation(ISO)aMin.width4.0bClearance to BN8.0umdClearance to DN9.0umBN4.bISO IslandISO4.adummy IslandDN4.d4.c2um 18V设计规则例 N+Emittera 1 Min.width 4.0 um i PBAS extension NEMT 1.5um j Space NEMT 3.0 um IslandISO(BP)IR7.a8.bBN8.cDNPBASSNSN8.aXBAS8.e8.d8.g8.i8.hSN8.j8.fNPN Transistor8.h8.i PBAS XBAS NEMTisland8.a2um 18V设计规则例 contacta1 Min.Width 2.0umb XBAS extension BCONT 1.0umNPNXBASSNBCONTTOPBAS10.a1,210.b10.c10.d10.e10.cBCONTNEMTBCONTTOBCONTTOBCONTTO10.a22um 18V设计规则例 Metala Min.width 3.0ume Space 2.0um under 500um parallel linef Space 3.0um Over 500um parallel lineM112.aSN12.c12.f12.eCO12.gPAD12.hM1M112.iCAP12.dBrief Process flow&Mask Sequence 1 Starting material2 Initial oxidation3 Buried N photo/etch4 BN implant5 BN drive-in6 Buried P photo7 BP implant8 Epi growth9 Initial oxidation10 Deep N+photo/etch11 POCl3 pre-deposition and oxidationBrief Process flow&Mask Sequence 12*Pbase photo13*PBAS implant14*Implanter resistor photo15*Resistor implant16*Extrinsic Pbase photo17*XBAS implant18 Drive-in19 N Emitter photo/etch20 NEMT implant21 NEMT drive-in22 Capacitor photo/etchBrief Process flow&Mask Sequence 23 Capacitor oxidation24 Si3N4 deposition25 Contact photo/etch26 Metal1 deposition27 Metal1 photo/etch28 Oxide deposition29 Via photo/etch30 Metal2 deposition31 Metal2 photo/etch33 USG/SiN Deposition33 Pad photo/etch34 Alloy制版信息光刻机类型和光刻版大小制版工具（图形发生器，电子束制版）版材料（石英，低膨胀玻璃）制版精度芯片和划片槽尺寸套准和CD标记PCM图形插入方案制版信息Process BiasMask Name Process Bias Digit.Scribe1BN-0.8umCD2BP(island)1.0umDC3DN-1.0CD4PBAS 0CC7NEMT-0.6umCD9CONT-0.5umCC10M1 0DCPCM（三）PN结隔离双极工艺流程（2um 18V）双极IC工艺流程N+埋层光刻和Sb+注入P(111)Sub10-20-cm75kev4.5E15cm-2双极IC工艺流程N+埋层扩散P 衬底N+埋层1225C 60N2+60O212+/-3/sq4.2umN+埋层版双极IC工艺流程P埋层光刻和B+离子注入P SubN+50kev 4E14cm-2P埋层版双极IC工艺流程外延P SubN-EpiN+埋层18V 8.0 0.5um 1.70.2cm36V 13.5 0.8um 4.3 0.43 cm外延层参数选择外延电阻率应主要满足BVbco的要求，可查BVNd曲线外延厚度 Xjbc+Wbc+Wbn基区埋层XjbcWbcEpiWbn外延层的质量评价外延电阻率外延厚度畸埋层图形偏移，畸变及对策缺陷（特别在有埋层图形处）双极IC工艺流程外延后氧化DN光刻磷予淀积(5.40.5/sq)磷扩散P SubN-EpiN+埋层DN版双极IC工艺流程去除全部氧化层，重新生长PAD氧化层P SubN-EpiN+埋层双极IC工艺流程基区(PBAS)光刻和B+注入B+注入P SubN-EpiN+埋层80kev4.1E14cm-2基区版双极IC工艺流程外基区(XBAS)（隔离）光刻B+注入P SubN-EpiN+埋层80kev4.1E14cm-2光刻胶基区和非本征基区基区（本征基区），外基区（非本征基区，浓基区）非本征基区作用减小基区串联电阻（提高功率增益）减小噪声隔离（XBAS)版双极IC工艺流程基区（隔离）推进P SubN-EpiN+埋层Rs=2238/sqXj=1.5um单向隔离和对通隔离单向隔离和对通隔离对通隔离优点减少隔离时间（尤其在外延层厚时）减少横向扩散，从而可减少隔离区宽度上隔离和XBAS可合用一块版双极IC工艺流程发射区光刻磷注入扩散P SubN-EpiN+埋层Rs=7.90.8/sqXj=1.0um发射区版双极IC工艺流程制作电容基区发射区+氮化硅450A氧化硅1500A电容版双极IC工艺流程接触孔光刻P SubN-EpiN+埋层接触孔版双极IC工艺流程金属连线P SubN-EpiN+埋层金属1版通孔版金属2版双层金属布线压点（PAD）版工艺控制计划（例）工艺名称控制项目控制值抽样大小抽样频率外延厚度8.00.5um5点/1片1片/Lot外延电阻率1.7 0.2cm5点/1片1片/LotDN予淀积方块电阻5.4 0.5/sq5点/1片2片/Run基区推进氧化层厚6000 600A5点/1片2片/Run基区推进方块电阻223 8/sq5点/1片1片/Lot发射光刻ADI CD4.0 0.4um5点/1片1片/Lot发射光刻AEI CD4.6 0.5um5点/1片1片/Lot（四）先进双极工艺双极型晶体管尺寸的缩小氧化物隔离双极工艺多晶硅发射极双极工艺双极型晶体管尺寸的缩小氧化物隔离的双极晶体管氧化物隔离双极工艺氧化物隔离双极工艺氧化物隔离双极工艺多晶硅发射极晶体管多晶硅发射极晶体管杂质分布多晶硅发射极双极工艺(1)多晶硅发射极双极工艺(2)多晶硅发射极双极工艺(3)模拟双极IC工艺特点(1)器件特性的精度要求高组成差分对的晶体管特性如,Vbe一致性好要求晶体管有较大的放大倍数100要求输出晶体管有较大的驱动能力 Vce(sat)小,例：0.11-0.21mV(Ic=1mA,Ib=100uA)要求晶体管的线性度好 (1uA)/(100uA)例：70-110%模拟双极IC工艺特点(2)pnp晶体管 横向和纵向pnp晶体管电容 大容量 MOS电容0.35-0.5fF/um2电阻 宽范围 扩散电阻10-100/sq 注入电阻0.5-2 k/sq夹断电阻 5-20 k/sq纵向pnp晶体管P Sub P+埋层P+P+n+基区nn-epin+埋层（五）工艺和器件模拟在工艺设计中的应用双极工艺模拟(SUPREM3)TITLE:Bipolar Device(SB20A):Active Region.#Initialize the silicon substrate.Initialize Silicon Boron Resistivity=15 Thick=10.dX=.02 xdX=.05 Spaces=200#Grow initial oxidation=7500ADiffusion Temperature=1100 Time=70 WetO2#Etch the oxide over the buried layer regions.Etch Oxide#Grow implanted oxide(175A)for BN layer oxidationDiffusion Temperature=875 Time=20 DryO2#Implant and drive-in the antimony buried layer Implant Antimony Dose=4.8e15 Energy=75Diffusion Temperature=1225 Time=360 N2Diffusion Temperature=1225 Time=120 DryO2双极工艺模拟(SUPREM3)Etch Oxide#Grow 9.5 micron of phosphorus doped epi.Epitaxy Temperature=1180 Time=13 Growth.Rate=0.8 Phosphorus Gas.Conc=3e15#EPI initial oxidationDiffusion Temperature=1100 Time=120 WetO2#ISO photo#ISO implant oxidationDiffusion Temperature=1000 Time=200 DryO2#ISO implant Implant Boron Dose=5E15 Energy=130#ISO pre-driveDiffusion Temperature=1175 Time=180 Nitrogen#ISO driveDiffusion Temperature=1100 Time=60 WetO2 双极工艺模拟(SUPREM3)#Deep collector pre-depDiffusion Temperature=980 Time=45 c.phosphorus=5e18#Getter oxidationDiffusion Temperature=900 Time=60 DryO2#Deep collector driveDiffusion Temperature=1200 Time=150 DryO2#Oxide removalEtch oxide#ReoxidationDiffusion Temperature=1100 Time=30 DryO2Diffusion Temperature=1100 Time=95 WetO2#Etch the oxide for base regionEtch Oxide双极工艺模拟(SUPREM3)#Move the fine grid to the surface.Grid Layer.1 Xdx=0.#Grow oxide for base implantDiffusion Temperature=1000 Time=25 WetO2#Implant the boron base.Implant Boron Dose=3E14 Energy=120#Base diffution Diffusion Temperature=1175 Time=30 NitrogenDiffusion Temperature=1175 Time=25 DryO2#Dope Emitter Diffusion Temperature=980 Time=30 c.phosphorus=1e21双极工艺模拟(SUPREM3)#Remove oxide from emitter region.Etch Oxide#Emitter oxidationDiffusion Temperature=875 Time=5 DryO2Diffusion Temperature=875 Time=120 WetO2Diffusion Temperature=875 Time=10 DryO2etch oxideTonyPlot -ttitle sbssb04.in:Final Bipolar Active Region#Save the resulting active region.Structure outfile=s3ex04.strElectrical Bias layer=1 region=2End.Elecprint layer双极工艺模拟(SUPREM3)杂质分布双极IC工艺器件模拟双极IC工艺-器件模拟
