74HC595中文资料,74HC595D规格书,74HC595N技术文档,DAT.pdf

DATA SHEETDATA SHEETProduct specificationSupersedes data of 1998 Jun 042003 Jun 25INTEGRATED CIRCUITS74HC595;74HCT5958-bit serial-in,serial or parallel-outshift register with output latches;3-state2003 Jun 252Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595FEATURES 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz(typical)shift out frequency ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.APPLICATIONS Serial-to-parallel data conversion Remote control holding register.DESCRIPTIONThe74HC/HCT595arehigh-speedSi-gateCMOSdevicesand are pin compatible with low power Schottky TTL(LSTTL).They are specified in compliance with JEDECstandard no.7A.The 74HC/HCT595 is an 8-stage serial shift register with astorage register and 3-state outputs.The shift register andstorage register have separate clocks.Data is shifted on the positive-going transitions of theSH_CP input.The data in each register is transferred tothe storage register on a positive-going transition of theST_CP input.If both clocks are connected together,theshift register will always be one clock pulse ahead of thestorage register.The shift register has a serial input(DS)and a serialstandard output(Q7)for cascading.It is also providedwith asynchronous reset(active LOW)for all 8 shiftregister stages.The storage register has 8 parallel 3-statebus driver outputs.Data in the storage register appears atthe output whenever the output enable input(OE)is LOW.QUICK REFERENCE DATAGND=0 V;Tamb=25 C;tr=tf=6 ns.Notes1.CPD is used to determine the dynamic power dissipation(PDin W).PD=CPD VCC2 fi N+(CL VCC2 fo)where:fi=input frequency in MHz;fo=output frequency in MHz;CL=output load capacitance in pF;VCC=supply voltage in Volts;N=total load switching outputs;(CL VCC2 fo)=sum of the outputs.2.For 74HC595 the condition is VI=GND to VCC.For 74HCT595 the condition is VI=GND to VCC 1.5 V.SYMBOLPARAMETERCONDITIONSTYPICALUNIT74HC74HCTtPHL/tPLHpropagation delayCL=50 pF;VCC=4.5 VSH_CP to Q71925nsSH_CP to Qn2024nsMR to Q710052nsfmaxmaximum clock frequency SH_CP and ST_CP10057MHzCIinput capacitance3.53.5pFCPDpower dissipation capacitance per packagenotes 1 and 2115130pF深圳市万瑞尔科技有限公司，NXP代理商，WWW.WONREAL.NET 0755-282697892003 Jun 253Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595FUNCTION TABLESee note 1.Note1.H=HIGH voltage level;L=LOW voltage level;=LOW-to-HIGH transition;=HIGH-to-LOW transition;Z=high-impedance OFF-state;n.c.=no change;X=dont care.ORDERING INFORMATIONINPUTOUTPUTFUNCTIONSH_CPST_CPOEMRDSQ7QnXXLLXLn.c.a LOW level on MR only affects the shift registersXLLXLLempty shift register loaded into storage registerXXHLXLZshift register clear;parallel outputs in high-impedanceOFF-stateXLHHQ6n.c.logic high level shifted into shift register stage 0;contents of all shift register stages shifted through,e.g.previous state of stage 6(internal Q6)appears on theserial output(Q7)XLHXn.c.Qncontents of shift register stages(internal Qn)aretransferred to the storage register and parallel outputstagesLHXQ6Qncontents of shift register shifted through;previouscontents of the shift register is transferred to thestorage register and the parallel output stagesTYPE NUMBERPACKAGETEMPERATURERANGEPINSPACKAGEMATERIALCODE74HC595N40 to+125 C16DIP16plasticSOT38-474HCT595N40 to+125 C16DIP16plasticSOT38-474HC595D40 to+125 C16SO16plasticSOT109-174HCT595D40 to+125 C16SO16plasticSOT109-174HC595DB40 to+125 C16SSOP16plasticSOT338-174HCT595DB40 to+125 C16SSOP16plasticSOT338-174HC595PW40 to+125 C16TSSOP16plasticSOT403-174HCT595PW40 to+125 C16TSSOP16plasticSOT403-174HC595BQ40 to+125 C16DHVQFN16plasticSOT763-174HCT595BQ40 to+125 C16DHVQFN16plasticSOT763-12003 Jun 254Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595PINNINGPINSYMBOLDESCRIPTION1Q1parallel data output2Q2parallel data output3Q3parallel data output4Q4parallel data output5Q5parallel data output6Q6parallel data output7Q7parallel data output8GNDground(0 V)9Q7serial data output10MRmaster reset(active LOW)11SH_CPshift register clock input12ST_CPstorage register clock input13OEoutput enable(active LOW)14DSserial data input15Q0parallel data output16VCCpositive supply voltagehandbook,halfpageQ1Q2Q3Q4Q5Q6Q7Q7Q0DSGNDST_CPSH_CPVCCOE12345678161514131211109595MLA001MRFig.1Pin configuration DIP16,SO16 and(T)SSOP16.handbook,halfpage116GND(1)Q1VCC823457Q2Q3Q4Q5Q615141312106119GNDTop viewMBL893Q7Q7MRSH_CPST_CPOEDSQ0Fig.2 Pin configuration DHVQFN16.(1)The die substrate is attached to this pad using conductive dieattach material.It can not be used as a supply pin or input.2003 Jun 255Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,halfpageOEMR91512345671310141112MLA002Q1Q0Q2Q3Q4Q5Q6Q7Q7DSST_CPSH_CPFig.3 Logic symbol.handbook,halfpageMSA69815912345671D2DC1/101114C21213EN3SRG8R3OEMRQ1Q0Q2Q3Q4Q5Q6Q7Q7DSST_CPSH_CPFig.4 IEC logic symbol.handbook,full pagewidthST_CPDSSH_CPMRQ78-STAGE SHIFT REGISTER8-BIT STORAGE REGISTER141110129OE3-STATE OUTPUTSQ1Q2Q3Q5Q6Q7Q4Q015123456713MLA003Fig.5 Functional diagram.2003 Jun 256Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,full pagewidthSTAGE 0STAGES 1 to 6STAGE 7FF0DCPQRLATCHDCPQFF7DCPQRLATCHDCPQMLA010DQQ1Q2Q3Q4Q5Q6Q7Q7Q0DSST_CPSH_CPOEMRFig.6 Logic diagram.2003 Jun 257Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,full pagewidthhigh-impedance OFF-stateST_CPDSSH_CPMROEQ1Q0Q7Q6Q7MLA005-1Fig.6 Timing diagram.2003 Jun 258Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595RECOMMENDED OPERATING CONDITIONSLIMITED VALUESIn accordance with the Absolute Maximum Rating System(IEC 60134);voltages are referenced to GND(ground=0 V).Note1.For DIP16 packages:above 70 C derate linearly with 12 mW/K.For SO16 packages:above 70 C derate linearly with 8 mW/K.For SSOP16 packages:above 60 C derate linearly with 5.5 mW/K.For TSSOP16 packages:above 60 C derate linearly with 5.5 mW/K.For DHVQFN16 packages:above 60 C derate linearly with 4.5 mW/K.SYMBOLPARAMETERCONDITIONS74HC74HCTUNITMIN.TYP.MAX.MIN.TYP.MAX.VCCsupply voltage2.05.06.04.55.05.5VVIinput voltage0VCC0VCCVVOoutput voltage0VCC0VCCVTambambient temperature40+12540+125Ctr,tfinput rise and fall timeVCC=2.0 V1000nsVCC=4.5 V6.05006.0500nsVCC=6.0 V400nsSYMBOLPARAMETERCONDITIONSMIN.MAX.UNITVCCsupply voltage0.5+7.0VIIKinput diode currentVI VCC+0.5 V20mAIOKoutput diode currentVO VCC+0.5 V20mAIOoutput source or sink currentVO=0.5 V to VCC+0.5 VQ7 standard output25mAQn bus driver outputs35mAICC,IGNDVCC or GND current70mATstgstorage temperature65+150CPtotpower dissipationTamb=40 to+125 C;note 1500mW2003 Jun 259Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595DC CHARACTERISTICSType 74HCAt recommended operating conditions;voltages are referenced to GND(ground=0 V).SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITOTHERVCC(V)Tamb=40 to+85 C;note 1VIHHIGH-level inputvoltage2.01.51.2V4.53.152.4V6.04.23.2VVILLOW-level inputvoltage2.00.80.5V4.52.11.35V6.02.81.8VVOHHIGH-level outputvoltageVI=VIH or VILall outputsIO=20 A2.01.92.0V4.54.44.5V6.05.96.0VQ7 standard outputIO=4.0 mA4.53.844.32VIO=5.2 mA6.05.345.81VQn bus driver outputsIO=6.0 mA4.53.844.32VIO=7.8 mA6.05.345.81VVOLLOW-level outputvoltageVI=VIH or VILall outputsIO=20 A2.000.1V4.500.1V6.000.1VQ7 standard outputIO=4.0 mA4.50.150.33VIO=5.2 mA6.00.160.33VQn bus driver outputsIO=6.0 mA4.50.160.33VIO=7.8 mA6.00.160.33VILIinput leakage currentVI=VCCor GND6.01.0AIOZ3-state outputOFF-state currentVI=VIHor VIL;VO=VCCor GND6.05.0AICCquiescent supplycurrentVI=VCCor GND;IO=06.080A2003 Jun 2510Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595Note1.All typical values are measured at Tamb=25 C.Tamb=40 to+125 CVIHHIGH-level inputvoltage2.01.5V4.53.15V6.04.2VVILLOW-level inputvoltage2.00.5V4.51.35V6.01.8VVOHHIGH-level outputvoltageVI=VIH or VILall outputsIO=20 A2.01.9V4.54.4V6.05.9VQ7 standard outputIO=4.0 mA4.53.7VIO=5.2 mA6.05.2VQn bus driver outputsIO=6.0 mA4.53.7VIO=7.8 mA6.05.2VVOLLOW-level outputvoltageVI=VIH or VILall outputsIO=20 A4.50.1VQ7 standard outputIO=4.0 mA4.50.4VQn bus driver outputsIO=6.0 mA4.50.4VILIinput leakage currentVI=VCCor GND5.51.0AIOZ3-state outputOFF-state currentVI=VIHor VIL;VO=VCCor GND5.510.0AICCquiescent supplycurrentVI=VCCor GND;IO=05.5160ASYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITOTHERVCC(V)2003 Jun 2511Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595Type 74HCTAt recommended operating conditions;voltages are referenced to GND(ground=0 V);tr=tf=6 ns;CL=50 pF.SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITOTHERVCC(V)Tamb=40 to+85 C;note 1VIHHIGH-level inputvoltage4.5 to 5.52.01.6VVILLOW-level inputvoltage4.5 to 5.51.20.8VVOHHIGH-level outputvoltageVI=VIHor VILall outputsIO=20 A4.54.44.5VQ7 standard outputIO=4.0 mA4.53.844.32VQn bus driver outputsIO=6.0 mA4.53.74.32VVOLLOW-level outputvoltageVI=VIHor VILall outputsIO=20 A4.500.33VQ7 standard outputIO=4.0 mA4.50.150.33VQn bus driver outputsIO=6.0 mA4.50.160.33VILIinput leakage currentVI=VCCor GND5.51.0AIOZ3-state outputOFF-state currentVI=VIHor VIL;VO=VCCor GND5.55.0AICCquiescent supplycurrentVI=VCCor GND;IO=05.580AICCadditional supplycurrent per inputVI=VCC 2.1 V;IO=0;note 24.5 to 5.5100450A2003 Jun 2512Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595Notes1.All typical values are measured at Tamb=25 C.2.The value of additional quiescent supply current(ICC)for a unit load of 1 is given here.To determine ICCper input,multiply this value by the unit load coefficient per input pin:a.pin DS:0.25b.pins MR,SH_CP,ST_CP and OE:1.50.Tamb=40 to+125 CVIHHIGH-level inputvoltage4.5 to 5.52.0VVILLOW-level inputvoltage4.5 to 5.50.8VVOHHIGH-level outputvoltageVI=VIHor VILall outputsIO=20 A4.54.4VQ7 standard outputIO=4.0 mA4.53.7VQn bus driver outputsIO=6.0 mA4.53.7VVOLLOW-level outputvoltageVI=VIHor VILall outputsIO=20 A4.50.1VQ7 standard outputIO=4.0 mA4.50.4VQn bus driver outputsIO=6.0 mA4.50.4VILIinput leakage currentVI=VCCor GND5.51.0AIOZ3-state outputOFF-state currentVI=VIHor VIL;VO=VCCor GND5.510.0AICCquiescent supplycurrentVI=VCCor GND;IO=05.5160AICCadditional supplycurrent per inputVI=VCC 2.1 V;IO=0;note 24.5 to 5.5490ASYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITOTHERVCC(V)2003 Jun 2513Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595AC CHARACTERISTICSFamily 74HCGND=0 V;tr=tf=6 ns;CL=50 pF.SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITWAVEFORMSVCC(V)Tamb=25 CtPHL/tPLHpropagation delaySH_CP to Q7see Fig.72.052160ns4.51932ns6.01527nspropagation delayST_CP to Qnsee Fig.82.055175ns4.52035ns6.01630nstPHLpropagation delayMR to Q7see Fig.102.047175ns4.51735ns6.01430nstPZH/tPZL3-state output enable timeOE to Qnsee Fig.112.047150ns4.51730ns6.01426nstPHZ/tPLZ3-state output disable timeOE to Qnsee Fig.112.041150ns4.51530ns6.01226nstWshift clock pulse widthHIGH or LOWsee Fig.72.07517ns4.5156ns6.0135nsstorage clock pulse widthHIGH or LOWsee Fig.82.07511ns4.5154ns6.0133nsmaster reset pulse widthLOWsee Fig.102.07517ns4.5156.0ns6.0135.0nstsuset-up time DS to SH_CPsee Fig.92.05011ns4.5104.0ns6.09.03.0nsset-up timeSH_CP to ST_CPsee Fig.82.07522ns4.5158ns6.0137nsthhold time DS to SH_CPsee Fig.92.0+36ns4.5+32ns6.0+32ns2003 Jun 2514Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595tremremoval time MR to SH_CP see Fig.102.0+5019ns4.5+107ns6.0+96nsfmaxmaximum clockpulse frequencySH_CP or ST_CPsee Figs 7 and 82.0930MHz4.53091MHz6.035108MHzTamb=40 to+85 CtPHL/tPLHpropagation delaySH_CP to Q7see Fig.72.0200ns4.540ns6.034nspropagation delayST_CP to Ansee Fig.82.0220ns4.544ns6.037nstPHLpropagation delayMR to Q7see Fig.102.0220ns4.544ns6.037nstPZH/tPZL3-state output enable timeOE to Qnsee Fig.112.0190ns4.538ns6.033nstPHZ/tPLZ3-state output disable timeOE to Qnsee Fig.112.0190ns4.538ns6.033nstWshift clock pulse widthHIGH or LOWsee Fig.72.095ns4.519ns6.016nsstorage clock pulse widthHIGH or LOWsee Fig.82.095ns4.519ns6.016nsmaster reset pulse widthLOWsee Fig.102.095ns4.519ns6.016nstsuset-up time DS to SH_CPsee Fig.92.065ns4.513ns6.011nsset-up timeSH_CP to ST_CPsee Fig.82.095ns4.519ns6.016nsSYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITWAVEFORMSVCC(V)2003 Jun 2515Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595thhold time DS to SH_CPsee Fig.92.03ns4.53ns6.03nstremremoval time MR to SH_CP see Fig.102.065ns4.513ns6.011nsfmaxmaximum clockpulse frequencySH_CP or ST_CPsee Figs 7 and 82.04.8MHz4.524MHz6.028MHzTamb=40 to+125 CtPHL/tPLHpropagation delaySH_CP to Q7see Fig.72.0240ns4.548ns6.041nspropagation delayST_CP to Qnsee Fig.82.0265ns4.553ns6.045nstPHLpropagation delayMR to Q7see Fig.102.0265ns4.553ns6.045nstPZH/tPZL3-state output enable timeOE to Qnsee Fig.112.0225ns4.545ns6.038nstPHZ/tPLZ3-state output disable timeOE to Qnsee Fig.112.0225ns4.545ns6.038nstWshift clock pulse widthHIGH or LOWsee Fig.72.0110ns4.522ns6.019nsstorage clock pulse widthHIGH or LOWsee Fig.82.0110ns4.522ns6.019nsmaster reset pulse widthLOWsee Fig.102.0110ns4.522ns6.019nsSYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITWAVEFORMSVCC(V)2003 Jun 2516Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595tsuset-up time DS to SH_CPsee Fig.92.075ns4.515ns6.013nsset-up timeSH_CP to ST_CPsee Fig.82.0110ns4.522ns6.019nsthhold time DS to SH_CPsee Fig.92.03ns4.53ns6.03nstremremoval time MR to SH_CP see Fig.102.075ns4.515ns6.013nsfmaxmaximum clockpulse frequencySH_CP or ST_CPsee Figs 7 and 82.04MHz4.520MHz6.024MHzSYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITWAVEFORMSVCC(V)2003 Jun 2517Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595Family 74HCTGND=0 V;tr=tf=6 ns;CL=50 pF.SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITWAVEFORMSVCC(V)Tamb=25 CtPHL/tPLHpropagation delaySH_CP to Q7see Fig.74.52542nspropagation delayST_CP to Qnsee Fig.84.52440nstPHLpr