基于VHDL语言的交通灯设计10321.pdf

动态扫描电路；LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY CTL IS PORT (reset :IN STD_LOGIC;clk :IN STD_LOGIC;TL,TS,TY,S :IN STD_LOGIC;ST :out std_logic;CODE_OUT :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);END CTL;ARCHITECTURE a OF CTL IS SIGNAL state:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN CODE_OUT if TL=1 AND S=1 then state=01;ST=1;else state=00;ST if TY=1 then state=10;ST=1;else state=01;ST if TS=1 OR S=0 then state=11;ST=1;else state=10;ST if TY=1 then state=00;ST=1;else state=11;STNULL;end case;END IF;end process;END a;时间电路；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY TIME IS PORT(CLK,ST:IN STD_LOGIC;TL,TS,TY:OUT STD_LOGIC );END TIME;ARCHITECTURE A OF TIME IS SIGNAL S60:INTEGER RANGE 0 TO 59;SIGNAL S30:INTEGER RANGE 0 TO 29;SIGNAL S5:INTEGER RANGE 0 TO 4;BEGIN PROCESS(CLK,ST)BEGIN IF CLKEVENT AND CLK=1 THEN IF ST=1 THEN S60=0;TL=0;ELSIF S60=59 THEN TL=1;ELSE S60=S60+1;END IF;END IF;END PROCESS;PROCESS(CLK,ST)BEGIN IF CLKEVENT AND CLK=1 THEN IF ST=1 THEN S30=0;TS=0;ELSIF S30=29 THEN TS=1;ELSE S30=S30+1;END IF;END IF;END PROCESS;PROCESS(CLK,ST)BEGIN IF CLKEVENT AND CLK=1 THEN IF ST=1 THEN S5=0;TY=0;ELSIF S5=4 THEN TY=1;ELSE S5dengdengdengdengnull;end case;end process;end a;