veriloghdl电子琴课程设计.docx
veriloghdl电子琴课程设计 XX学院 课程设计报告 题 目 Verilog hdl课程设计 专 业 自动化 学生姓名 指导老师 完成时间 2015 课程设计（报告）任务书 （理 工 科 类） 课程设计（报告）题目： 电子琴的设计 课程设计（论文）工作内容 一、课程设计目标 1、培育综合运用学问和独立开展实践创新的实力； 2、深化学习Verilog HDL，了解其编程环境； 3、学会运用Modelsim和Quartus II等编程仿真软件； 4、将硬件语言编程与硬件实物功能演示相结合，加深理解Verilog HDL的学习； 二、探讨方法及手段应用 1、将任务分成若干模块，查阅相关论文资料，分模块调试和完成任务； 2、遇到问题小组成员刚好探讨得出解决方法； 3、遇到本组内解决不了的问题，刚好和其他小组沟通或询问老师； 4、程序仿真，仿真无问题后进行模块调试，依据试验箱上的硬件实现是否符合要求来检验程序正确与否。 三、课程设计预期效果 1、完成试验环境搭建； 2、具有手动弹奏和自动播放功能； 3、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶； 4、自动播放曲目至少两首； 摘 要 简易电子琴的设计通过通过软硬件结合实现，硬件系统包括主控器芯片、9个按键、LED、蜂鸣器等，软件资源包括编写Verilog HDL程序的应用软件Modelsim和仿真软件Quartus II。电子琴有按键代替琴键的弹奏功能和自动播放功能。按键有七个音，自动播放功能中有三首曲子，分别是两只老虎、天空之城和康定情歌。程序共有五个模块，分别为主模块、琴键模块、曲1模块、曲2模块、曲3模块。硬件实现是用三个LED灯组合亮暗分别表示七个按键按下状况，另外两个按键用来选择曲目。试验箱原始时钟为50MHz，分频后变成不同的频率输出，通过蜂鸣器输出不同频率的声音。音乐的节拍通过分频变为4Hz，作为1/4拍。通过主模块调用各模块实现电子琴的功能。 Verilog HDL 电子琴 模块 分频 ABSTRACT This article introduced the simple electric pianos design. It realizes through the software and hardware union. The hardware system includes a director, 9 keys, LEDs and a buzzer. The software design uses Verilog HDL. Emulation uses Quartus II. It can broadcast the system establishment the corresponding note, and can complete a military song the broadcast, but also has shows the sound the function. Designs the simple electric piano to have in the hardware. The program has seven modules, including main module, fractional frequency module and so on. Keyboard with keys to play the function and replace the keys to play function. Key has seven sound, automatic playback function with three in song, were the two tiger “, “the sky city“ and “kangding love songs. Software has its merit. It is perfect in the software Verilog HDL. The original frequency is divided into different frequencys. The piano makes sound by the buzzer with different frequencys. Verilog HDL electric piano module fractional frequency 第一章 系统设计 第一节 课题目标及总体方案 本次项目设计课程的目标是让我们在学习Verilog HDL的基础上更加深化的理解硬件设计语言的功能、作用及其特征，并且将我们的动手实力与创新实力结合起来。本次电子琴试验的目标是： 1、具有手动弹奏和自动播放功能； 2、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶； 3、自动播放曲目至少两首； 本次试验的方框图为：（每个模块中都有分频） 主模块 九个键 Key1到Key7用于弹奏 Key8与Key9（mm）用于选择歌曲 mm=00 按键模块 Key1 到 Key7 模块名digital_piano mm=01 曲目1两只老虎 模块名 bell mm=10 曲目2康定情歌 模块名 bell2 mm=11 曲目3天空之城 模块名 bell3 其次节 设计框图说明 一、 主模块 主模块中用mm=(key8,key9)值的不同选择调用不同模块，mm=01调用曲目1模块，即bell模块；mm=10调用曲目2模块，即bell2模块；mm=11调用曲目3模块，即bell3模块；而在key8与key9没有被按下的状况下，程序调用按键模块，即digital_piano模块 module main(inclk,outclk,key1,key2,key3,key4,key5,key6,key7,key8,key9,num); input inclk; input key1,key2,key3,key4,key5,key6,key7,key8,key9; output outclk; output3:0num; reg outclk,clk_6M; reg 3:0c; wire out1,out2,out3,out4; wire8:0 key; reg 1:0mm; assign key = key1,key2,key3,key4,key5,key6,key7,key8,key9; /由按键拼键为变量key /调用子调块 digital_piano m1(.inclk(inclk),.key1(key1),.key2(key2),.key3(key3),.key4(key4), .key5(key5),.key6(key6),.key7(key7),.beep2(out2),.num(num); bell m2(.inclk(inclk),.beep1(out1); bell2 m3(.inclk(inclk),.beep3(out3); bell3 m4(.inclk(inclk),.beep4(out4); always (posedge clk_6M) /在时钟的上升沿检测是否有按键按下 begin if(key = 9b111111110) mm <= 2b01; else if(key=9b111111101) mm <= 2b10; else if(key=9b111111100) mm <= 2b11; else mm <= 2b00; end always(posedge inclk) begin if(c<4d4) c<=c+4d1; else begin c<=4d0; clk_6M=clk_6M; end end always (posedge clk_6M) begin if(mm = 2b01) outclk <= out1; else if(mm = 2b00) outclk <= out2; else if(mm = 2b10) outclk <= out3; else outclk <= out4; end endmodule 二、按键模块 Key1到key7对应do到si七个音，用于模拟电子琴弹奏 /digital_piano子模块 module digital_piano(inclk,key1,key2,key3,key4,key5,key6,key7,beep2,num); input inclk,key1,key2,key3,key4,key5,key6,key7; output3:0num; output beep2; wire 6:0 key_code; reg 3:0c; reg clk_6M; reg beep_r; reg 3:0num; reg 15:0 count; reg 15:0 count_end; parameter Do = 7b1111110, /状态机的7个编码，分别对应中音的7个音符 re = 7b1111101, mi = 7b1111011, fa = 7b1110111, so = 7b1101111, la = 7b1011111, si = 7b0111111; assign key_code = key7,key6,key5,key4,key3,key2,key1; assign beep2 = beep_r; /输出音乐 always(posedge inclk) begin if(c<4d4) c<=c+4d1; else begin c<=4d0; clk_6M=clk_6M; end end always(posedge clk_6M) /分频模块，得出乐谱 begin count <= count + 16d1; /计数器加1 if(count = count_end) begin count <=16d0; /计数器清零 beep_r <= !beep_r; end end always(posedge clk_6M) /状态机，依据按键状态，选择不同的音符输出 begin case(key_code) Do: count_end <= 16d11450; re: count_end <= 16d10204; mi: count_end <= 16d09090; fa: count_end <= 16d08571; so: count_end <= 16d07802; la: count_end <= 16d06802; si: count_end <= 16d06060; default:count_end <= 16d0; endcase end always (posedge clk_6M) begin case(key_code) Do: num<=4b0001; re: num<=4b0010; mi: num<=4b0011; fa: num<=4b0100; so: num<=4b0101; la: num<=4b0110; si: num<=4b0111; endcase end endmodule 二、 曲目1模块 /bell子模块 两只老虎 module bell (inclk,beep1); input inclk; /系统时钟 output beep1; /蜂鸣器输出端 reg 3:0high,med,low; reg 15:0origin; reg beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep1=beep_r; /输出音乐 /时钟频率6MHz reg clk_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt1<3d4) cnt1<=cnt1+3b1; else begin cnt1<=3b0; clk_6MHz<=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedge inclk) begin if(cnt2<25d6250000) cnt2<=cnt2+25b1; else begin cnt2<=25b0; clk_4Hz<=clk_4Hz; end end always (posedge clk_6MHz) begin count <= count + 1b1; /计数器加1 if(count = origin) begin count <= 16h0; /计数器清零 beep_r <= !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) 12b000000010000:origin=11466;/mid1 12b000000100000:origin=10216;/mid2 12b000000110000:origin=9101;/mid3 12b000001000000:origin=8590;/mid4 12b000001010000:origin=7653;/mid5 12b000001100000:origin=6818;/mid6 12b000000000101:origin=14447;/low5 endcase end always (posedge clk_4Hz) /歌曲 <<two tiger>> begin if(state =63) state = 0;/计时，以实现循环演奏 else state = state + 1; case(state) 0,1: high,med,low=12b000000010000;/mid1 2,3: high,med,low=12b000000100000;/mid2 4,5: high,med,low=12b000000110000;/mid3 6,7: high,med,low=12b000000010000;/mid1 8,9: high,med,low=12b000000010000;/mid1 10,11: high,med,low=12b000000100000;/mid2 12,13: high,med,low=12b000000110000;/mid3 14,15: high,med,low=12b000000010000;/mid1 16,17: high,med,low=12b000000110000;/mid3 18,19: high,med,low=12b000001000000;/mid4 20,21,22,23: high,med,low=12b000001010000;/mid5 24,25: high,med,low=12b000000110000;/mid3 26,27: high,med,low=12b000001000000;/mid4 28,29,30,31: high,med,low=12b000001010000;/mid5 32: high,med,low=12b000001010000;/mid5 33: high,med,low=12b000001100000;/mid6 34: high,med,low=12b000001010000;/mid5 35: high,med,low=12b000001000000;/mid4 36,37: high,med,low=12b000000110000;/mid3 38,39: high,med,low=12b000000010000;/mid1 40: high,med,low=12b000001010000;/mid5 41: high,med,low=12b000001100000;/mid6 42: high,med,low=12b000001010000;/mid5 43: high,med,low=12b000001000000;/mid4 44,45: high,med,low=12b000000110000;/mid3 46,47: high,med,low=12b000000010000;/mid1 48,49: high,med,low=12b000000100000;/mid2 50,51: high,med,low=12b000000000101;/low5 52,53,54,55: high,med,low=12b000000010000;/mid1 56,56: high,med,low=12b000000100000;/mid2 57,58: high,med,low=12b000000000101;/low5 59,60,61,62,63: high,med,low=12b000000010000;/mid1 default : high,med,low=12bx; endcase end endmodule 三、 曲目2模块 /bell2子模块康定情歌 module bell2 (inclk,beep3); input inclk; /系统时钟 output beep3; /蜂鸣器输出端 reg 3:0high,med,low; reg 15:0origin; reg beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep3=beep_r; /输出音乐 /时钟频率6MHz reg clk_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt1<3d4) cnt1<=cnt1+3b1; else begin cnt1<=3b0; clk_6MHz<=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedge inclk) begin if(cnt2<25d6250000) cnt2<=cnt2+25b1; else begin cnt2<=25b0; clk_4Hz<=clk_4Hz; end end always (posedge clk_6MHz) begin count <= count + 1b1; /计数器加1 if(count = origin) begin count <= 16h0; /计数器清零 beep_r <= !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) b000000000001:origin=22900; /低1 b000000000010:origin=20408; /低2 b000000000011:origin=18181; /低3 b000000000101:origin=15267; /低5 b000000000110:origin=13605; /低6 b000000000111:origin=11472; /中1 b000000100000:origin=10216; /中2 b000000110000:origin=9101; /中3 b000001010000:origin=7653; /中5 b000001100000:origin=6818; /中6 b000100000000:origin=5733; /高1 b001000000000:origin=5108; /高2 b001100000000:origin=4551; /高3 endcase end always (posedge clk_4Hz) begin if(state =103) state = 0; else state = state + 1; /康定情歌 case(state) 0,1: high,med,low=b000000110000;/中3 2,3: high,med,low=b000001010000;/中5 4,5: high,med,low=b000001100000;/中6 6: high,med,low=b000001100000;/中6 7: high,med,low=b000001010000;/中5 8,9,10: high,med,low=b000001100000;/中6 11: high,med,low=b000000110000;/中3 12,13,14,15: high,med,low=b000000100000;/中2 16,17: high,med,low=b000000110000;/中3 18,19: high,med,low=b000001010000;/中5 20,21: high,med,low=b000001100000;/中6 22: high,med,low=b000001100000;/中6 23: high,med,low=b000001010000;/中5 24,25: high,med,low=b000001100000;/中6 26,27,28,29,30,31:high,med,low=b000000110000;/中3 32,33: high,med,low=b000000110000;/中3 34,35: high,med,low=b000001010000;/中5 36,37: high,med,low=b000001100000;/中6 38: high,med,low=b000001100000;/中6 39: high,med,low=b000001010000;/中5 40,41,42: high,med,low=b000001100000;/中6 43: high,med,low=b000000110000;/中3 44,45,46,47: high,med,low=b000000100000;/中2 48,49: high,med,low=b000000000101;/中5 50,51: high,med,low=b000000110000;/中3 52: high,med,low=b000000100000;/中2 53: high,med,low=b000000110000;/中3 54: high,med,low=b000000100000;/中2 55: high,med,low=b000000000111;/1 56,57: high,med,low=b000000100000;/中2 58,59,60,61,62,63:high,med,low=b000000000110;/低6 64,65: high,med,low=b000001100000;/中6 66,67,68,69,70,71:high,med,low=b000000100000;/中2 72,73: high,med,low=b000000000101;/中5 74,75,76,77,78,79:high,med,low=b000000110000;/中3 80: high,med,low=b000000100000;/中2 81: high,med,low=b000000000111;/1 82,83,84,85,86,87:high,med,low=b000001100000;/中6 88,89: high,med,low=b000000000101;/中5 90,91: high,med,low=b000000110000;/中3 92: high,med,low=b000000100000;/中2 93: high,med,low=b000000110000;/中3 94: high,med,low=b000000100000;/中2 95: high,med,low=b000000000111;/1 96,97: high,med,low=b000000100000;/中2 98,99,100,101,102,103:high,med,low=b000001100000;/中6 endcase end endmodule 四、 曲目3模块 /bell3子模块天空之城 module bell3 (inclk,beep4); input inclk; /系统时钟 output beep4; /蜂鸣器输出端 reg 3:0high,med,low; reg 15:0origin; reg beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep4=beep_r; /输出音乐 /时钟频率6MHz reg clk_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt1<3d4) cnt1<=cnt1+3b1; else begin cnt1<=3b0; clk_6MHz<=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedge inclk) begin if(cnt2<25d6250000) cnt2<=cnt2+25b1; else begin cnt2<=25b0; clk_4Hz<=clk_4Hz; end end always (posedge clk_6MHz) begin count <= count + 1b1; /计数器加1 if(count = origin) begin count <= 16h0; /计数器清零 beep_r <= !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) b000000000001:origin=22900; /低1 b000000000010:origin=20408; /低2 b000000000011:origin=18181; /低3 b000000000100:origin=17142; /低4 b000000000101:origin=15267; /低5 b000000000110:origin=13605; /低6 b000000000111:origin=12121; /低7 b000000000111:origin=11472; /中1 b000000100000:origin=10216; /中2 b000000110000:origin=9101; /中3 b000000111000:origin=8571; /中4 b000001010000:origin=7653; /中5 b000001100000:origin=6818; /中6 b000010000000:origin=6060; /中7 b000100000000:origin=5733; /高1 b001000000000:origin=5108; /高2 b001100000000:origin=4551; /高3 b001010000000:origin=4294; /高4 b010000000000:origin=3826; /高5 b011000000000:origin=3409; /高6 b010100000000:origin=3050; /高7 endcase end always (posedge clk_4Hz) begin if(state =195)state = 0; else state = state + 1; /kang ding qing ge case(state) 0: high,med,low=b000001100000;/中6 1: high,med,low=b000010000000;/中7 2,3,4: high,med,low=b000100000000;/高1 5: high,med,low=b000010000000;/中7 6,7: high,med,low=b000100000000;/高1 8,9: high,med,low=b001100000000;/高3 10,11,12,13,14,15: high,med,low=b000010000000;/中7 16,17: high,med,low=b00000011000
