ESD保护设计研讨会(英文).pptx

California Micro Devices2023/4/10 上午 12:04:54 1ESD Protection Design Seminar Jim SutherlandSenior Applications EngineerCalifornia Micro Devices2023/4/10 上午 12:04:54 2Outline4 What is ESD?4 What damage can it cause?4 Why is the problem growing?4 What are the issues for the designer?4 How can we measure it?4 How can we protect equipment from ESD?California Micro Devices2023/4/10 上午 12:04:54 3What Is ESD?4ESD=Electro Static Discharge4Generation-Triboelectric(friction causes accumulation of charge)-Induction(field induces charge)4Discharge-Dielectric(air)breakdown Electric field increases when charged bodies approach each other-Current flow into circuitry California Micro Devices2023/4/10 上午 12:04:54 4ESD Damage of ICs4Permanent-Oxide breakdown,shorts,opens,latch-up4Temporary-Latch-up,ground bounce4Latent-Degradation from an ESD eventCalifornia Micro Devices2023/4/10 上午 12:04:54 5 ESD problem is growing4Circuits/Systems-Old -Robust ICs&Low speed signals-New -Sensitive ICs&High speed signals4Environment-Old -Manufacturing/Corporate-New -Home/Outdoors/PersonCalifornia Micro Devices2023/4/10 上午 12:04:54 6ESD Issues for the Designer 4Must meet ESD specifications4Select ESD tolerant components4Minimize signal degradation(from R,L&C)4Board space/weight/proper design4Component cost4Assembly cost4Lifetime cost (stability)4Test the systemCalifornia Micro Devices2023/4/10 上午 12:04:54 7International ESD Standards4Human Body Model(HBM)-for devices-EIA/JESD22-A114-A-ANSI/EOS/ESD-S5.1-1993-MIL-STD-883(method 3015)4IEC 1000-4-2:1995 -for systems4Machine Model(MM)-less common-EIA/JESD22-A115-A-ANSI/EOS/ESD-S5.1-19934Charge Device Model(CDM)-less common-JESD22-c101California Micro Devices2023/4/10 上午 12:04:54 8Human Body Model(HBM)4Discharge from 100pF capacitor through 1.5 kOhm resistor46 ESD pulses-3 positive,3 negative-1 sec separation4Pin-to-pin testing-N(N-1)/2 combinations4Used for component characterization4Widely usedCalifornia Micro Devices2023/4/10 上午 12:04:54 9HBM Current WaveformRise Time:2 nS Tr 10 nSCalifornia Micro Devices2023/4/10 上午 12:04:54 10IEC 1000-4-2:1995 Standard4Discharge from 150 pF capacitor through 330 ohm resistor46 ESD pulses-3 positive,3 negative4Used for system characterization4“Contact”v.“Air”discharge-Different levels-Different applicationsCalifornia Micro Devices2023/4/10 上午 12:04:54 11IEC 1000-4-2 Current WaveformVery fast rise time:Tr 1nS60nsCalifornia Micro Devices2023/4/10 上午 12:04:54 12IEC 1000-4-2 Test Levels4Contact discharge is the preferred test method-air discharges are not repeatable4Air discharges used where contact discharge cannot be applied4No implied equivalence in test severity between the two test methodsCalifornia Micro Devices2023/4/10 上午 12:04:54 13IEC 1000-4-2 Bench Test SpecificationCalifornia Micro Devices2023/4/10 上午 12:04:54 14ESD Protection Techniques4Clamp diodes in IC-Not sufficient protection 4Shielding -Low effectiveness4Bypass capacitor or series resistor/inductor-Can degrade signal;many components;large board area 4Spark gap-Low cost;low stability;large board area4Discrete Zener diodes-High capacitance,many components;large board area4Discrete PN diodes-Low capacitance;many components;large board area 4Integrated PN diodesCalifornia Micro Devices2023/4/10 上午 12:04:54 15Integrated Diode Networks4Superior downstream ESD protection-High speed response-ESD current steered to GND or VCC4Minimum Signal Degradation(Low C)4Minimal board space,weight4Low assembly/manufacturing costs4Minimal Design-In Time4Long-term reliabilityCalifornia Micro Devices2023/4/10 上午 12:04:54 16Choosing an ESD Diode Network4How many lines are needed?4How much capacitance?(e.g.5 pF)4What is the HBM rating?(e.g.15 kV)4What is the downstream clamp voltage?(e.g.13 V 15 kV HBM pulse)4What is the contact discharge rating?(e.g.8 kV)4What is the air discharge rating?(e.g.15 kV)4What package?(e.g.24-pin QSOP)California Micro Devices2023/4/10 上午 12:04:55 17ESD Diode Network PlacementThe Need to Keep ESD DiodesDownstream of Line InductancesAlso put protection diodes at most likely ESD entry point-the connectorPreferred LayoutESD EntryPointParasitic LVccGndProtectedDevicePoor layout-increased clamp voltagedue to parasitic inductanceParasitic LVccGndProtectedDeviceESD EntryPointCalifornia Micro Devices2023/4/10 上午 12:04:55 18Designing for Minimal PowerRail InductanceCalifornia Micro Devices2023/4/10 上午 12:04:55 19Add Bypass Capacitor-Place Ceramic bypass capacitor(0.1 0.2 uF)as close as possible to ESD diode network power rail to shunt ESD current to both power rails-Maybe add Zener in parallel with capacitor to minimize parasitic inductance of bypass capacitorProtectedDeviceGndVccCCalifornia Micro Devices2023/4/10 上午 12:04:55 20Using a Series Resistor toMinimize Downstream Current4Can be considered for latch-up sensitive applications4Guaranteed clamping voltage limits current downstream(I=V/R)4Only for inputs with high Z4Only for output drivers with low Z-watch out for filtering of signalCalifornia Micro Devices2023/4/10 上午 12:04:55 21Power-down Issues4Diode protected systems that are powered down can drain current from an active high input through the diode to VCC 4This can drain batteries and/or damage devices on the same line4To avoid this,isolate VCC from the bypass capacitor with a blocking diode4One diode solutionCalifornia Micro Devices2023/4/10 上午 12:04:55 22Component and System Specifications4There is no simple formula to translate system specifications into component specifications-IEC 1000-4-2 Specification is more severe than HBM-Line capacitance and inductance shape the ESD pulse,reducing its peak value-Poor device placement can degrade performance-If there are multiple devices on a line,decide which to protect-The relationship between downstream clamp voltage and downstream protection is not exactCalifornia Micro Devices2023/4/10 上午 12:04:55 23Validating the Design4Define the practical limits of functional failure(e.g.Data integrity,recovery time)4Test only at those places subject to touch during normal operation4Use Contact ES Discharges to coupling planes&conductive surfaces,I/O pins,flex pads,and power pins 4Use Air ES Discharges to insulating surfaces,openings at edges of keys,flex cables,vent areas,seams,slots,aperturesCalifornia Micro Devices2023/4/10 上午 12:04:55 24Total Solution Cost4ESD failure is a question of statistics4One cannot eliminate all reliability issues4Goal is to minimize total solution cost-Cost of reliability-Cost of protection4Must find proper minimumCalifornia Micro Devices2023/4/10 上午 12:04:55 25Lightning vs.ESD-200MV 30kA 30us 15kV 45A 80nS