第七章同步电路.ppt

SoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬第七章第七章同步电路设计及与异步同步电路设计及与异步信号交互问题信号交互问题OutlineSynchronous Design vs.Asynchronous DesignAsynchronous Interface nMetastabilitynSlow clock domain to fast clock domainnFast clock domain to slow clock domainGeneral Clock Strategy About Synchronous DesignWhat is synchronous design circuit?nAll clocked element,such as flip flops(FFs)or registers,share a common clock signal(a globally distributed clock)nData changes based on clk edgesnExample:clk reaches to R1 and R2 at the same time How to guarantee synchronous design for millions of gates in layout?Clock Tree Synthesis(CTS)supported by EDA company used to solve the problemClock Tree Synthesis CTS tool will do:nParasitic extractionnDelay calculationnTiming analysisnPlacementnRoutingTopologies:nH treen.Pros and ConsProsnFully supported by EDA toolsnStatic timing analysis tools are designed to report timing problem on one-clock synchronous designsnEasy to implementConsnNoise caused by the gates on the clock path nClock skew nIncreased chip areanIncreased powerAbout Asynchronous DesignTransition can be done at any time-Not controlled by any global or local clockAsynchronous Design cont.Designing a purely asynchronous circuit is a nontrivial and potentially hazardous tasknHow to avoid race and hazard conditions?nNot supported by EDA toolsnHandshaking protocols result in complexityOutlineSynchronous Design vs.Asynchronous DesignAsynchronous Interface nMetastabilitynSlow clock domain to fast clock domainnFast clock domain to slow clock domainGeneral Clock Strategy MetastabilityObserved:nasynchronous inputs in synchronous systems lead to system failure(also called synchronization failure)Metastability-contAn asynchronous input which can change at any time with respect to the clock edges of the synchronous system.When a FF input signal is changing state at or near the instant of active clk edge occurring.Metastable statenThe output of the device does not reach either of the valid logic levels but between the two for a time that is long compared with the normal timing delays of the device or may even oscillate.nIf the signal bdat1 is propagated to the rest of the design before it comes to a stable state,synchronous failure will occur.More cases in real ASIC design world nInput data from UART,SSI,devices to another device/chipnAsynchronous external reset Metastability-contAvoid Metastability Case I Case 1:signal from slow CLK domain enter into fast CLK domainCommon approach is 2 stage FF synchronizer Extra clock cycle added to delay.This must be acceptable in application if this type of solution is chosen Two Stage FF SynchronizerTwo FFs Synchronizer cont.Two Stage FF Synchronizer cont.But a synchronizer does not eliminate the possibility of metastable failure.It only limits its occurrence within the synchronizer and thereby minimize its effect on the system Bad news-building a perfect synchronizer that always delivers a legal answer is impossible!MTBF Mean time between failures(MTBF)for a single flip-flop:MTBF=(nsec)T :the period of the synchronizing clock Ts:is the setting timel:the mean rate of arrival of data edgestand To:describe the metastability performance of the flip-flopA Shift Register Synchronizer:A chain of(N+1)flip-flops Assumed that a metastable state is transferred along the chain of flip-flops by simple sampling Simplified Equation tp is the propagation delay of a flip-flopThe more stage,the more stable.But introduce longer delay MTBF=Avoid Metastability Case IICase II:Signal from Fast Clock Domain into Slow Clock DomainProblem:a signal from a fast clock domain only asserted for one fast clock cycle before it can be sampled into a slow clock domain.Can not solve the problem!If using 2 stage FF synchronizer:Common Practical Solution Handshaking ProtocolExample 1:To assert control signal for a period of time that exceeds the cycle time of the sampling clk(hand shaking)Data-Path SynchronizationPassing multi-bit data from one clk domain to anotherA Common mistake:nTry to apply a simple synchronized flip-flop approach to synchronizing bused signals.Problem:nNo guarantee that the bus data alignment is preserved.(This could be due to the different loading on each bit of data.)Consequently,bus data are incorrectly sampled Common practical solutions:nTo have a data_valid signals accompany the bus(handshaking)nUse asynchronous FIFO(First In First Out memories)Data-Path Synchronization cont.Method 1:to have a data_valid signal accompany the bus nData_valid signal is not asserted until a comfortable timing margin after all the bus bits have transitioned.nTo synchronize data_valid signal only and use it to indicate Bus bits are stable nCondition:the rate of sampling clk must be much higher than the rate of updates on the BusData-Path Synchronization cont.Method 2:use FIFOs nDual port memory:dual port SRAM or FF arraynThe data first written to it shall also be the first one read from itnStore(write)data using one clk domain and retrieve(read)data using another clk domainWhat is FIFOInitial state4 data have been written in fifo,but none has been read 4 data are written in fifo,while one data has been read FIFO StructureAsynchronous Signals in FIFO Design FIFO can not be read when there is no data in it -emptyFIFO can not be written when the number of data in it reaches FIFO depth fullFIFO full or empty signals are generated by 2 address pointers,wptr and rptr,which are generated from 2 different clk domains,wclk and rclk respectively.nwptr and rptr are asynchronous signals FIFO Design:Asynchronous Case cont.Suggestion:n FIFO pointers implemented as Gray-code counter which only change one bit at a timenExample of binary and Gray codes:Binary code:00,01,10,11Gray code:00,01,11,10nWill either be the old value or the new value if asynchronous signal comes in the middle of a Gray code counter transitionnThe Gray-code pointers are synchronized by the clock from the opposite clock domain to generate FIFO full/empty flags wptr=rptr FIFO empty wptr+1=rptr FIFO fullOutlineSynchronous Design vs.Asynchronous DesignAsynchronous Interface nMetastabilitynSlow clock domain to fast clock domainnFast clock domain to slow clock domainGeneral Clock Strategy General Clock Strategy for SoC DesignPrefer synchronous designnThe tools for logic synthesis and Clock Tree Synthesis do their best work on synchronous designnStatic timing analysis tools are designed to report timing problem on one-clock synchronous designsnThe task of DFT scan insertion is simplifiedGeneral Clock Strategy-contUse the smallest number of clk domainsnProblem with more clk domainsnComplicate synthesis scriptsnFalse path,multi cycle pathn Complicate DFT scan insertionnSeparated scan chainsnIncrease the possibility of encountering metastabilityClock Strategy for SoC Design-contTry to group asynchronous design,if there is,any into separate modulesnEasily identify them in backend design and given special treatmentnEasy for design reviewGeneral Clock Strategy cont.Avoid latchesnLatch:level-sensitivenTransparent during its on timenAdvantage:fast(clock rate can be higher than the worst case critical path)nAllowing one stage to pass slack or to borrow time from other stagenComplicated to perform STA due to the ability of being transparent when enablednA latch input is an end point when latch is closed but effectively a midpoint if the latch is opennDifficult for DFT implementation if mixed with FFsGeneral Clock Strategy-contMinimize clock latencynLarge clock latency on a global clk may introduced when trying to minimize clock skew in a large designnLatency can cause functional failure and extra power consumptionInterface between clk domains should avoid metastablityTrendsLarge high-speed integrated circuits will eventually need to be designed without global clockingFully Asynchronous DesignCan we do without a clock altogether?In theory:certainlyIn reality:not likely any time soonGlobally Asynchronous Locally Synchronous(GALS)Alternative:multiple local synchronous clock domains:nCustom design of clock domain interfacesnBusiness as usual with the domainsSoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬Thank youQ&A