基于eda的智能函数发生器课程设计说明书--大学论文.doc

邮电与信息工程学院课程设计说明书课题名称： 电子设计自动化（EDA）课程设计 一、课程设计的任务的基本要求：1.设计目的：() 学习使用设计软件Quartus，了解电路描述、综合、模拟过程。() 掌握使用工具设计数字系统的设计思路和设计方法。2.设计要求：()以Altera DE2开发系统为验证平台，根据设计题目要求完成设计输入、综合、仿真与验证工作。() 提供设计报告，报告要求包括以下内容：设计任务书、题目、摘要（中英文）、正文、参考文献。其中正文应包含：设计思路、设计输入文件、设计与调试过程、仿真与验证结果和设计结论。3.设计题目：()设计智能函数发生器，要求实现正弦波、方波、三角波、递增、递减斜波和阶梯波六种波形，所产生的波形频率用数码管显示。 二、进度安排：18周（2009.6.82009.6.12）：周一：选择课程设计题目，明确课程设计目的和任务。周二、周三：查看参考资料。周四、周五：原理图与程序设计。19周（2009.6.152008.6.19）：周一、周二：上机调试原理图与程序。周三：整理所有任务资料，答辩。周四、周五：撰写课程设计报告。三、应收集资料及主要参考文献：（1） Altera DE2 User Manual（2） 基于Quartus II的FPGA/CPLD数字系统设计实例，周润景等，电子工业出版社（3） EDA技术实用教程（第二版），潘松等，科学出版社四、课程设计摘要（中文）：函数发生器是一种很常用的器件，在很多情况下，最常用的波形是正弦波，方波，三角波，递增，递减斜波和阶梯波六种。虽然用模拟电子线路很容易得到这些波形，但是这种方法会使硬件线路较为繁琐，而且模拟线路会受到干扰。本设计采用综合设计方法使用FPGA来实现智能函数发生器，它由六个波形产生模块及波形选择输出模块组成，波形选择模块的输出q接在D/A转换的数据端，就可以在D/A输出端得到想要的其中之一的任一种光滑的波形五、课程设计摘要（英文）：The function generator is one kind of very commonly used component, In very many situations,The most commonly used profile is a sine wave,Square-wave,Triangle wave,Increases progressively,Decreases progressively the wave tilt and the steps and ladders wave six kinds. Although is very easy with the simulation electronic circuit to obtain these profiles, But this method can cause the hardware line to be tedious,Moreover the artificial line can receive the disturbance. This design uses FPGA to realize the intelligence function generator,It has the module and the profile choice output module by six profiles is composed, Profile choice module output q meets in D/A transforms data end, May in the D/A out-port obtains one of them which wants no matter what one kind of smooth profile.正文一、设计思路1.基于QUASTUS II平台，采用VHDL语言，设计一波形信号发生器。首先根据对各波形的幅度进行采样，获得各波形的波形数据表，使用FPGA来实现智能函数发生器，它由六个波形产生模块及波形选择输出模块组成，然后FPGA根据输入的时钟（频率可根据要求可变）作为地址信号，从FPGA数据线上输出相应的波形数据，再送入实验板上的D/A转换芯片进行转换为模拟信号，最后送入滤波电路滤波后输出，就可以得到想要的任意其中的一个波形二、设计输入文件与调试分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity fenpin isport (clk: in std_logic; clkfen: out std_logic); end fenpin;architecture fenpin of fenpin issignal clk_mid: std_logic;begin process(clk) variable data:integer range 0 to 99; begin if clk'event and clk='1' then if data=99 then data:=0; clk_mid<=not clk_mid; else data:=data+1;end if;end if;clkfen<=clk_mid;end process;end fenpin;2.递减波形数据产生模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY dj IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END dj;ARCHITECTURE behave OF dj ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset='0'THEN tmp:="11111111" ELSIF clk'EVENT AND clk='1'THEN IF tmp="00000000"THEN Tmp:="11111111" ELSE tmp:=tmp-1; END IF;END IF; q<=tmp; END PROCESS;END behave; 3.递增（锯齿波）波形数据产生模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY dz IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END dz;ARCHITECTURE behave OF dz ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset='0'THEN tmp:="00000000" ELSIF clk'EVENT AND clk='1'THEN IF tmp="11111111"THEN tmp:="00000000" ELSE tmp:=tmp+1; END IF; END IF;q<=tmp; END PROCESS;END behave;4.方波波形数据产生模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;ENTITY fb IS PORT (clk,reset: IN STD_LOGIC; q:OUT INTEGER RANGE 0 TO 255);END fb; ARCHITECTURE behave OF fb ISSIGNAL a: BIT;BEGIN PROCESS (clk,reset) VARIABLE cnt: INTEGER range 0 to 31; BEGIN IF reset='0'THEN A<='0' ELSIF clk'EVENT AND clk='1'THEN IF cnt<31 THENCnt:=cnt+1; ELSE cnt:=0; a<=NOT a;END IF; END IF; END PROCESS; Process (clk,a) BEGINIF clk'EVENT AND clk='1'THEN IF a='1'THEN Q<=255; ELSE Q<=0; END IF; END IF;END PROCESS;END behave；5.三角波波形数据产生模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jcb IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END jcb;ARCHITECTURE behave OF jcb ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE a: STD_LOGIC; BEGIN IF reset='0'THEN tmp:="00000000" ELSIF clk'EVENT AND clk='1'THEN IF a='0'THENIF tmp="11111110"THEN tmp:="11111111" a:='1' ELSE tmp:=tmp+1; END IF;ELSE IF tmp="00000001"THEN tmp:="00000000" a:='0'ELSE tmp:=tmp-1; END IF; END IF;END IF;q<=tmp; END PROCESS;END behave6.阶梯波形数据产生模块设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtb isport(clk,reset:in std_logic;q:out std_logic_vector(7 downto 0);end jtb;architecture a of jtb isbeginprocess(clk,reset)variable tmp:std_logic_vector(7 downto 0);beginif reset='0' thentmp:="00000000"else if clk'event and clk='1' thenif tmp="11111111" thentmp:="00000000"elsetmp:=tmp+16;end if;end if;end if;q<=tmp;end process;end a;7.正弦波波形数据产生模块设计library ieee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zx is port(clk:in std_logic; reset:in std_logic; q:out std_logic_vector(7 downto 0);end zx;architecture behav of zx is signal b:integer range 0 to 63; signal d:integer range 0 to 255;beginprocess(clk)begin if reset='0'then b<=0; elsif clk'event and clk='1' then if b=63 then b<=0; else b<=b+1; end if; end if; end process; process(b) begin case b is when 00=>d<=255;when 01=>d<=254; when 02=>d<=252; when 03=>d<=249; when 04=>d<=245; when 05=>d<=239; when 06=>d<=233; when 07=>d<=225; when 08=>d<=217; when 09=>d<=207; when 10=>d<=197; when 11=>d<=186; when 12=>d<=174; when 13=>d<=162; when 14=>d<=150; when 15=>d<=137; when 16=>d<=124; when 17=>d<=112;when 18=>d<=99; when 19=>d<=87; when 20=>d<=75; when 21=>d<=64; when 22=>d<=53; when 23=>d<=43; when 24=>d<=34; when 25=>d<=26; when 26=>d<=19; when 27=>d<=13;when 28=>d<=8; when 29=>d<=4; when 30=>d<=1; when 31=>d<=0;when 32=>d<=0; when 33=>d<=1; when 34=>d<=4; when 35=>d<=8; when 36=>d<=13; when 37=>d<=19; when 38=>d<=26; when 39=>d<=34; when 40=>d<=43; when 41=>d<=53; when 42=>d<=64; when 43=>d<=75; when 44=>d<=87; when 45=>d<=99; when 46=>d<=112; when 47=>d<=124; when 48=>d<=137; when 49=>d<=150; when 50=>d<=162; when 51=>d<=174; when 52=>d<=186; when 53=>d<=197; when 54=>d<=207; when 55=>d<=217; when 56=>d<=225; when 57=>d<=233; when 58=>d<=239; when 59=>d<=245; when 60=>d<=249; when 61=>d<=252; when 62=>d<=254; when 63=>d<=255;when others=>null; end case; end process; q<=conv_std_logic_vector(d,8);end behav;8.六选一选择器模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;ENTITY xz IS PORT (sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0); d0,d1,d2,d3,d4,d5: IN STD_LOGIC_VECTOR(7 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END xz;ARCHITECTURE behave OF xz ISBEGIN PROCESS (sel) BEGIN CASE sel IS WHEN "000" =>q<=d0; WHEN "001" =>q<=d1; WHEN "010" =>q<=d2; WHEN "011" =>q<=d3; WHEN "100" =>q<=d4; WHEN "101" =>q<=d5; WHEN OTHERS =>NULL; END CASE; END PROCESS; END behave; 9译码library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.std_logic_unsigned.all;entity ym is port( clk,rst :in std_logic; data :in std_logic_vector(7 downto 0); sel :out std_logic_vector(2 downto 0); data_disp:out std_logic_vector(6 downto 0);end ym;architecture RTL of ym issignal count :integer range 9 downto 0;signal temp :integer range 4 downto 0;signal number_h,number_t,number_l:integer range 0 to 9;begin process(data,clk,rst)beginif(rst='0')then number_h<=0; number_t<=0; number_l<=0;elsif(to_integer(unsigned(data)>=200 AND to_integer(unsigned(data)-200>=50)then number_h<=2; number_t<=5; number_l<=to_integer(unsigned(data)-250;elsif(to_integer(unsigned(data)>=200 AND to_integer(unsigned(data)-200>=40)then number_h<=2; number_t<=4;number_l<=to_integer(unsigned(data)-240;elsif(to_integer(unsigned(data)>=200 AND to_integer(unsigned(data)-200>=30)then number_h<=2; number_t<=3; number_l<=to_integer(unsigned(data)-230;elsif(to_integer(unsigned(data)>=200 AND to_integer(unsigned(data)-200>=20)then number_h<=2; number_t<=2; number_l<=to_integer(unsigned(data)-220;elsif(to_integer(unsigned(data)>=200 AND to_integer(unsigned(data)-200>=10)then number_h<=2; number_t<=1; number_l<=to_integer(unsigned(data)-210;elsif(to_integer(unsigned(data)>=200)then number_h<=2; number_t<=0; number_l<=to_integer(unsigned(data)-200;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=90)then number_h<=1; number_t<=9; number_l<=to_integer(unsigned(data)- 190;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=80)then number_h<=1; number_t<=8; number_l<=to_integer(unsigned(data)-180;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=70)then number_h<=1; number_t<=7; number_l<=to_integer(unsigned(data)-170;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=60)then number_h<=1; number_t<=6; number_l<=to_integer(unsigned(data)-160;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=50)then number_h<=1; number_t<=5; number_l<=to_integer(unsigned(data)-150;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=40)then number_h<=1; number_t<=4; 140;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=30)then number_h<=1; number_t<=3; number_l<=to_integer(unsigned(data)-130;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=20)then number_h<=1; number_t<=2; number_l<=to_integer(unsigned(data)-120;elsif(to_integer(unsigned(data)>=100 AND to_integer(unsigned(data)-100>=10)then number_h<=1; number_t<=1; number_l<=to_integer(unsigned(data)-110;elsif(to_integer(unsigned(data)>=100)then number_h<=1; number_t<=0; number_l<=to_integer(unsigned(data)-100;elsif(to_integer(unsigned(data)>=90)then number_h<=0; number_t<=9; number_l<=to_integer(unsigned(data)-90;elsif(to_integer(unsigned(data)>=80)then number_h<=0; number_l<=to_integer(unsigned(data)number_t<=8; number_l<=to_integer(unsigned(data)-80;elsif(to_integer(unsigned(data)>=70)then number_h<=0; number_t<=7; number_l<=to_integer(unsigned(data)-70;elsif(to_integer(unsigned(data)>=60)then number_h<=0; number_t<=6; number_l<=to_integer(unsigned(data)-60;elsif(to_integer(unsigned(data)>=50)then number_h<=0; number_t<=5; number_l<=to_integer(unsigned(data)-50;elsif(to_integer(unsigned(data)>=40)then number_h<=0; number_t<=4; number_l<=to_integer(unsigned(data)-40;elsif(to_integer(unsigned(data)>=30)then number_h<=0; number_t<=3; number_l<=to_integer(unsigned(data)-30;elsif(to_integer(unsigned(data)>=20)then number_h<=0; number_t<=2; number_l<=to_integer(unsigned(data)-20;elsif(to_integer(unsigned(data)>=10)then number_h<=0; number_t<=1; number_l<=to_integer(unsigned(data)-10;elsenumber_h<=0;number_t<=0;number_l<=to_integer(unsigned(data);end if;end process;process( clk,rst,temp,number_h,number_l) begin if(clk'event and clk='1')then if(temp=2)then temp<=0; else temp<=temp+1; end if; end if; case temp is when 0=>sel<="001" count<=number_l; when 1=>sel<="010" count<=number_t; when 2=>sel<="100" count<=number_h; when others=>NULL; end case;end process;process(count)begin case count iswhen 0=>data_disp<="1000000"when 1=>data_disp<="1111001"when 2=>data_disp<="0100100"when 3=>data_disp<="0110000"when 4=>data_disp<="0011001"when 5=>data_disp<="0010010"when 6=>data_disp<="0000010"when 7=>data_disp<="1111000"when 8=>data_disp<="0000000"when 9=>data_disp<="0010000"when others=>null;end case;end process;end RTL;三.设计原理图及仿真结果原理框图三角波模块递减斜波模块clkresetSel=0Sel=1选择 Sel=2Sel=3Sel=4Sel=5Sel2.0递增斜波模块正弦波模块方波模块阶梯波模块原理图总体仿真结果四.仿真与验证结果 递减波形仿真结果 递增波形仿真结果方波仿真结果阶梯波仿真结果三角波仿真结果正弦波仿真结果五、设计结论 运用VHDL 语言进行智能函数发生器功能的设计具有以下优势: 信号发生器的功能测试与仿真实验结果表明, 时序和波形正确, 达到了设计的功能要求。在信号量化的过程中, 可以实现任意模数的计数器, 如加、减计数, 可以方便的实现递增锯齿波和递减锯齿波的设计。为了智能化的选择不同信号的波形, 系统设计了波形选择调用模块, 来完成不同函数信号的输出。在设计过程中, 可以将一些常用的模块定义为相应的逻辑元件符号, 以便共享和复用, 使设计具有可重用性和可移植性, 可以实现一些复杂系统的设计, 提高工作效率。六、成绩评定：指导教师评语： 指导教师签字： 200 年 月 日项 目评价项 目评价调查论证工作量、工作态度实践能力分析、解决问题能力质 量创 新得 分七、答辩纪录：答辩意见及答辩成绩答辩小组教师（签字）： 200 年 月 日 总评成绩：（教师评分×75%+答辩成绩×25%）课程设计评审标准（指导教师用）评价内容具 体 要 求权 重调查论证 能独立阅读文献和从事其他调研；能提出并较好地论述课题实施方案；有收集、加工各种信息及获得新知识的能力。0.1实践能力 能正确选择研究（实验）方法，独立进行研究工作。如装置安装、调试、操作。0.2分析解决问题能力 能运用所学知识和技能去发现和解决实际问题；能正确处理实验数据；能对课题进行理论分析，得出有价值的结论。0.2工作量、工作态度 按期圆满完成规定任务，工作量饱满，难度较大，工作努力，遵守纪律；工作作风严谨务实。0.2质量 综述简练完整，有见解；立论正确，论述充分，结论严谨合理；实验正确，分析处理科学；文字通顺，技术用语准确，符号统一，编号齐全，书写工整规范，图表完备、整洁、正确；论文结果有应用价值。0.2创新 工作中有创新意识；对前人工作有改造或独特见解。0.1