数字电路英文版第十一单元.pptx
11.1 THE COMPLETE OLMC 11.1 THE COMPLETE OLMC In Chapter 7 the output logic macrocells(OLMC)for the GAL22V10 and the GAL16V8 were examined in terms of their combinational model,and the flip-flop contained in the OLMC was only briefly mentioned.2第1页/共103页 In this section,we will discuss the complete OLMC which includes a flip-flop,again using the GAL22V10 and the GAL16V8 as representative PLD devices.3第2页/共103页The Output Logic Macrocell(OLMC)in the GAL22V104Logic Diagram1-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1DQQCLKSPAR第3页/共103页5 The four OLMC configurations are Combinational mode with active-LOW outputCombinational mode with active-HIGH outputRegistered mode with active-LOW outputRegistered mode with active-HIGH output第4页/共103页1-of-4multiplexer1-of-3multiplexerFlip-FlopOLMCAC0*AC1(n)I/ODQQCLKSYN AC1(n)1-of-4multiplexer1-of-2MULTXORGAL16V8第5页/共103页6 11.2 OLMC MODE SELECTION 11.2 OLMC MODE SELECTION The Combination Mode:S1S0=10 or S1S0=11 The flip-flop is not used in the combinational mode.第6页/共103页81-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=1S0=0DQQCLKSPARS1=1(a)OLMC in the active-LOW combinational mode第7页/共103页9I/O(a)The effective logic diagram第8页/共103页101-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=1 S0=1DQQCLKSPARS1=1(b)OLMC in the active-HIGH combinational modeI/O第9页/共103页10I/O(b)The effective logic diagram第10页/共103页12 The Registered Mode:S1S0=00 or S1S0=01 第11页/共103页131-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=0S0=0DQQCLKSPARS1=0(a)OLMC in the active-LOW registered modeI/O第12页/共103页(a)The effective logic diagramFlip-FlopDQQSPARCLKI/O14第13页/共103页151-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=0S0=1DQQCLKSPARS1=0(b)OLMC in the active-HIGH registered modeI/O第14页/共103页(b)The effective logic diagramFlip-FlopDQQSPARCLKI/O16第15页/共103页17Software Mode Specification1.The ISTYPE statement is used to declare an output as either combinational or registered with the use of the attributes com or reg .Q0 PIN 23 ISTYPE reg;Q0 PIN 23 ISTYPE reg,buffer;第16页/共103页182.Q0:=D0;Q0 will assume the value of the D0 input on the clock.X=A;indicates that the output X is equal to the input A.第17页/共103页193.The dot extension.CLK is used to indicate that the register devices is a clocked flip-flop.Q0:=D0;must be followed by a clock equation such as Q0.CLK=Clock;第18页/共103页20EXAMPLE 11-1 Write the ABEL pin declarations and the equations to specify the GAL22V10 in Fig.11-6 as a parallel input/parallel output clocked register with D0 through D7 as inputs and Q0 through Q7 as registered outputs that are not inverted.第19页/共103页21OLMC1238OLMC22210OLMC21123OLMC2014OLMC1916OLMC1816654CLKGAL22V10D0D1D2D3D4Q0Q1Q2Q3Q4第20页/共103页22Solution The pin declaration statements can be written asClock,D0,D1,D2,D3,D4,D5,D6,D7 PIN 1,2,3,4,5,6,7,8,9;Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 PIN 22,21,20,19,18,17,16,15,ISTYPE reg,buffer The equations can be written using set notation as follows:Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 :=D0,D1,D2,D3,D4,D5,D6,D7;Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7.CLK=Clock;第21页/共103页Q0 :=D0;Q0.CLK =Clock;Q1 :=D1;Q1.CLK =Clock;Q2 :=D2;Q2.CLK =Clock;Q3 :=D3;Q3.CLK =Clock;Q4 :=D4;Q4.CLK =Clock;Q5 :=D5;Q5.CLK =Clock;Q6 :=D6;Q6.CLK =Clock;Q7 :=D7;Q7.CLK =Clock;23第22页/共103页 11.3 IMPLEMENTING SHIFT 11.3 IMPLEMENTING SHIFT REGISTERS WITH PLDsREGISTERS WITH PLDs In the last section,you learned about the registered mode and how the OLMC flip-flop is used.In this section,you will see how shift registers can be implemented with a PLD.Again,the GAL22V10 is used for illustration.24第23页/共103页25An 8-Bit Serial In/Parallel Out Shift RegisterD QCCLRD QCCLRD QCCLRD QCCLRD QCCLRD QCCLRD QCCLRD QCCLRQ0Q1Q2Q3Q4Q5Q6Q7ClockClearDataEnable第24页/共103页26Implementing the Shift Register with a PLDQ0:=Data&Enable;Q1 :=Q0;Q2 :=Q1;Q3 :=Q2;Q4 :=Q3;Q5 :=Q4;Q6 :=Q5;Q7 :=Q6;第25页/共103页27Developing the ABEL Input FileModule Eight_bit_shift_registerTitle 8-bit shift register in a GAL22V10 “Device Declaration Register device P22V10 “Pin Declaration Clock,Clear pin 1,2;Data,Enable pin 3,4;Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 pin 16,17,18,19,20,21,22,23 ISTYPE reg,buffer 第26页/共103页EquationsQ0:=Data&Enable;Q1,Q2,Q3,Q4,Q5,Q6,Q7 :=Q0,Q1,Q2,Q3,Q4,Q5,Q6;Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7.CLK =Clock;Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7.AR =!Clear;28第27页/共103页29Test_Vectors(Clock,Clear,Data,Enable Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7).x.,0 ,.x.,.x.0,0,0,0,0,0,0,0;.c.,1 ,1,0 0,0,0,0,0,0,0,0;.c.,1 ,0,1 0,0,0,0,0,0,0,0;.c.,1 ,1,1 1,0,0,0,0,0,0,0;.c.,1 ,0,1 0,1,0,0,0,0,0,0;.c.,1 ,1,1 1,0,1,0,0,0,0,0;.c.,1 ,0,1 0,1,0,1,0,0,0,0;.c.,1 ,1,1 1,0,1,0,1,0,0,0;.c.,1 ,0,1 0,1,0,1,0,1,0,0;.c.,1 ,1,1 1,0,1,0,1,0,1,0;.c.,1 ,0,1 0,1,0,1,0,1,0,1;第28页/共103页 .c.,1 ,1,1 1,0,1,0,1,0,1,0;.c.,1 ,0,1 0,0,0,0,0,0,0,0;END30第29页/共103页D QCCLRD QCCLRD QCCLRD QCCLRD0D1D2D3Q0Q1Q2Q3ClockClearSH/LDSerial output31第30页/共103页Solution The ABEL input file is as follows:Module Four_bit_shift_registerTitle 4-bit shift register in a GAL22V10 “Device Declaration Register device P22V10 “Pin Declaration Clock,Clear pin 1,2;SHLD pin 3;D0,D1,D2,D3 pin 4,5,6,7 ISTYPE reg,buffer Q0,Q1,Q2,Q3 pin 14,15,16,17 ISTYPE reg,buffer 32第31页/共103页EquationsQ0:=D0;Q1:=Q0&SHLD#D1&!SHLD;Q2:=Q1&SHLD#D2&!SHLD;Q3:=Q2&SHLD#D3&!SHLD;Q0,Q1,Q2,Q3.CLK=Clock;Q0,Q1,Q2,Q3.AR =!Clear;33第32页/共103页34Test_Vectors(Clock,Clear,SHLD,D0,D1,D2,D3 Q3 ).x.,0 ,.x.,.x.,.x.,.x.,.x.0 .c.,1 ,.0.,.0.,.1.,.0.,.1.1 .c.,1 ,.0.,.1.,.0.,.1.,.0.0 .c.,1 ,.1.,.1.,.0.,.1.,.0.1 .c.,1 ,.1.,.1.,.0.,.1.,.0.0 .c.,1 ,.1.,.1.,.0.,.1.,.0.1 .c.,0 ,.0.,.1.,.0.,.1.,.0.0 第33页/共103页35Related ProblemSolution The ABEL input file is as follows:Module Five_bit_shift_registerTitle 5-bit shift register in a GAL22V10 “Device Declaration Register device P22V10 “Pin Declaration Clock,Clear pin 1,2;SHLD pin 3;D0,D1,D2,D3,D4 pin 4,5,6,7,8 ISTYPE reg,buffer Q0,Q1,Q2,Q3,Q4 pin 14,15,16,17,18 ISTYPE reg,buffer 第34页/共103页36EquationsQ0:=D0;Q1:=Q0&SHLD#D1&!SHLD;Q2:=Q1&SHLD#D2&!SHLD;Q3:=Q2&SHLD#D3&!SHLD;Q0,Q1,Q2,Q3,Q4.CLK=Clock;Q0,Q1,Q2,Q3,Q4.AR =!Clear;Q4:=Q3&SHLD#D4&!SHLD;第35页/共103页 11.4 IMPLEMENTING 11.4 IMPLEMENTING COUNTERS WITH PLDsCOUNTERS WITH PLDs As you have learned,counters consist of flip-flops just as shift registers do;but counters have a prescribed sequence of states,whereas registers do not.In this section,the general types of state machines are discussed and three approaches to implementing a counter in a PLD are covered.37第36页/共103页38Combinational logicMemoryInputsOutputs(a)Moore state machine第37页/共103页Moore state machine:The output depend only on the internal state and any inputs that are synchronized with the circuit.Counters are examples of the Moore type of state machine.第38页/共103页39Combinational logicMemoryInputsOutputs(b)Mealy state machine第39页/共103页Mealy state machine:The outputs are depend by both the internal state and by inputs that are not synchronized with the circuit.第40页/共103页40A 3-bit Up/Down Gray Code Counter Design000110011101001010100111State diagram for a 3-bit Gray code counter.Y=1Y=0ABCDEFGH第41页/共103页41 Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0 Present State Next State 0 0 0 1 0 0 0 0 1 Y=0(DOWN)Y=1(UP)0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0Next-state table for the 3-bit up/down Gray code counter第42页/共103页42 QN QN+1 D Output Transition Flip-Flop Input 0 0 0Transition table for a D flip-flop.0 1 1 1 0 0 1 1 1第43页/共103页43Q2Q1Q0YQ2Q1Q0Y11111111111111100000000010101011111111110101010D0 mapD1 mapQ2Q1YQ2Q1YQ2Q1YQ2Q0YQ1Q0Q2Q0YQ0YQ2Q1Y1第44页/共103页44Q2Q111111110000010111111010D2 mapQ1Q0YQ2Q0Q1Q0Y1Q0Y第45页/共103页45The Boolean Expressions for the D InputsD0=Q2Q1Y+Q2Q1Y+Q2Q1Y+Q2Q1YD1=Q2Q0Y+Q2Q0Y+Q1Q0D2=Q1Q0Y+Q1Q0Y+Q2Q0Logic diagram of the 3-bit up/down Gray code counter in page 584 Figure 11-13.第46页/共103页46EXAMPLE 11-3:Module Three_bit_U/D_Gray_code_counterTitle 3-bit Gray Code Counter in a GAL22V10 “Device Declaration Counter device P22V10 “Pin Declaration Clock,Clear pin 1,2;Y pin 3;Q0,Q1,Q2 pin 21,22,23 ISTYPE reg,buffer;第47页/共103页47EquationsQ0:=Q2&Q1&Y#!Q2&!Q1&Y#Q2&!Q1&!Y#!Q2&Q1&!YQ1:=Q2&Q0&!Y#!Q2&Q0&Y#Q1&!Q0;Q2:=!Q1&!Q0&!Y#Q1&!Q0&Y#Q2&Q0;Q0,Q1,Q2.CLK=Clock;Q0,Q1,Q2.AR =!Clear;第48页/共103页48Test_Vectors(Clock,Clear,Y ,Q0,Q1,Q2).c.,0 ,.x.,0,0,0,;.c.,1 ,0,1,0,0,;.c.,1 ,0,1,0,1,;.c.,1 ,0,1,1,1,;.c.,1 ,0,1,1,0,;.c.,1 ,0,0,1,0,;.c.,1 ,0,0,1,1,;.c.,1 ,0,0,0,1,;.c.,1 ,0,0,0,0,;Down第49页/共103页49 .c.,1 ,1,0,0,1,;.c.,1 ,1,0,1,1,;.c.,1 ,1,0,1,0,;.c.,1 ,1,1,1,0,;.c.,1 ,1,1,1,1,;.c.,1 ,1,1,0,1,;.c.,1 ,1,1,0,0,;.c.,1 ,1,0,0,0,;up第50页/共103页50EXAMPLE 11-4:Develop an ABEL input file using the truth table format to implement the 3-bit up/down Gray code counter in Fig.11-13.A GAL22V10 is the target device.Module Three_bit_U/D_Gray_code_counter“Device Declaration Counter device P22V10 “Pin Declaration Title 3-bit Gray Code Counter in a GAL22V10 Clock,Clear pin 1,2;Y pin 3;第51页/共103页51 Q0,Q1,Q2 pin 21,22,23 ISTYPE reg,buffer;Equations Q0,Q1,Q2.CLK=Clock;Q0,Q1,Q2.AR =!Clear;第52页/共103页52Truth_Table(Clear,Y ,Q2,Q1,Q0 :Q2,Q1,Q0 ;)0 ,.x.,.x.,.x.,.x.:0,0,0 ;1 ,0 ,0,0,0 :1,0,0 ;1 ,0 ,1,0,0 :1,0,1 ;1 ,0 ,1,0,1 :1,1,1 ;1 ,0 ,1,1,1 :1,1,0 ;1 ,0 ,1,1,0 :0,1,0 ;1 ,0 ,0,1,0 :0,1,1 ;第53页/共103页 1 ,0 ,0,0,1 :0,0,0 ;1 ,1 ,0,0,0 :0,0,1 ;1 ,1 ,0,0,1 :0,1,1 ;1 ,1 ,0,1,1 :0,1,0 ;1 ,1 ,0,1,0 :1,1,0 ;1 ,1 ,1,1,0 :1,1,1 ;1 ,1 ,1,1,1 :1,0,1 ;1 ,1 ,1,0,1 :1,0,0 ;1 ,1 ,1,0,0 :0,0,0 ;1 ,0 ,0,1,1 :0,0,1 ;第54页/共103页Test_Vectors(Clock,Clear,Y ,Q0,Q1,Q2).c.,0 ,.x.,0,0,0,;.c.,1 ,0,1,0,0,;.c.,1 ,0,1,0,1,;.c.,1 ,0,1,1,1,;.c.,1 ,0,1,1,0,;.c.,1 ,0,0,1,0,;.c.,1 ,0,0,1,1,;.c.,1 ,0,0,0,1,;.c.,1 ,0,0,0,0,;Down54第55页/共103页 .c.,1 ,1,0,0,1,;.c.,1 ,1,0,1,1,;.c.,1 ,1,0,1,0,;.c.,1 ,1,1,1,0,;.c.,1 ,1,1,1,1,;.c.,1 ,1,1,0,1,;.c.,1 ,1,1,0,0,;.c.,1 ,1,0,0,0,;up55第56页/共103页Implementing the Counter with an ABEL State DiagramIF-THEN-ELSE Statements:IF Y THEN B ELSE H;The statement can also be written using lowercase letters.56第57页/共103页Defining the StatesQSTATE =Q2,Q1,Q0 This is followed by the name and values for the eight states.A =0,0,0 ;B =0,0,1 ;C =0,1,1 ;D =0,1,0 ;E =1,1,0 ;F =1,1,1 ;G =1,0,1 ;H =1,0,0 ;57第58页/共103页EXAMPLE 11-5 Develop an ABEL input file using the state diagram format to implement the 3-bit up/down Gray code counter in Figure 11-13.A GAL22V10 is the target device.Solution Notice that we still have the equations defining Clock and Clear.58第59页/共103页Module Three_bit_U/D_Gray_code_counter“Device Declaration Counter device P22V10 “Pin Declaration Title 3-bit Gray Code Counter in a GAL22V10 Clock,Clear pin 1,2;Y pin 3;Q0,Q1,Q2 pin 21,22,23 ISTYPE reg,buffer;59第60页/共103页“State Definitions QSTATE =Q2,Q1,Q0 ;A =0,0,0 ;B =0,0,1 ;C =0,1,1 ;D =0,1,0 ;E =1,1,0 ;F =1,1,1 ;G =1,0,1 ;H =1,0,0 ;EquationsQSTATE.CLK=Clock;QSTATE.AR =!Clear;60第61页/共103页State_diagram QSTATEState A:if Y then B else H;State B:if Y then C else A;State C:if Y then D else B;State D:if Y then E else C;State E:if Y then F else D;State F:if Y then G else E;State G:if Y then H else F;State H:if Y then A else G;Test vectors is same as example 11-4.61第62页/共103页 11.5 PLD SYSTEM IMPLEMENTATION11.5 PLD SYSTEM IMPLEMENTATION In this section,a specific example is used to illustrate the use of the state diagrams and other entry methods to implement a complete system with PLDs using ABEL.The examples system is an elevator control for a two-floor building and uses two GAL16V8 devices.62第63页/共103页The SystemState control logicGAL16V8Display logicGAL16V8LCKREQ1REQ2FLOOR2FLOOR1OPENARRIVEL1PBL1PB_L2PBL2PB_DOORMOTIONDIRFloor sensor switchPush_button inputsPush_button latch outputs7-segment floordisplayUp arrowDown arrow63第64页/共103页 Output Variable State DOOR 0=Open 1=Close MOTION 0=Wait 1=Move DIR 0=Up 1=DownTABLE 11-364第65页/共103页Inputs to the State Control LogicCLK :The clock signal establishes the length of time that the door remains open.The period of the clock is 10s.REQ1 :Request for the elevator to come to the first floor.(outside of the door)REQ2 :Request for the elevator to come to the second floor.(outside of the door)65第66页/共103页FLOOR2 :Instruction for the elevator to go to the second floor.(inside the elevator)FLOOR1 :Instruction for the elevator to go to the first floor.(inside the elevator)OPEN :Instruction for the door to open when the elevator is not moving.(inside the elevator)ARRIVE :Instruction that the elevator has arrived at a new floor.(Sensor switches)66第67页/共103页Outputs from the State Control LogicL1PB and L1PB_ :First floor latch outputs for push-button switches.L2PB and L2PB_ :Second floor latch outputs for push-button switches.DOOR :Controls the status of the elevator door.DOOR=0,open;DOOR=1,closed.67第68页/共103页DIR :Controls the direction of the movement.DIR=0,up;DIR=1,down.MOTION :Controls the movement of the elevator.MOTION=0,wait;MOTION=1,moving.68第69页/共103页The State Diagram for the Elevator State Control LogicREST1 :The elevator is waiting on the first floor with the door open.CLOSE1 :The elevator is waiting on the first floor with the door closed.UP :The elevator is moving from the first to second floor.69第70页/共103页REST2 :The elevator is waiting on the second floor with the door open.CLOSE2 :The elevator is waiting on the second floor with the door closed.DOWN :The elevator is moving from the second to first floor.70第71页/共103页RESET1000Door=0(open)MOTI=0(wait)DIR=0(up)CLOSE1100Door=1(closed)MOTI=0(wait)DIR=0(up)DOWN111Door=1(closed)MOTI=1(move)DIR=1(down)RESET2001Door=0(open)MOTI=0(wait)DIR=1(down)CLOSE2101Door=1(closed)MOTI=0(wait)DIR=1(down)UP110Door=1(closed)MOTI=1(move)DIR=0(up)ARRIVEARRIVEREQ1*FLOOR1REQ2*FLOOR2REQ1+FLOOR1REQ2+FLOOR2REQ2+OPENREQ1+OPENREQ1+FLOOR1REQ2+FLOOR271第72页/共103页Description of OperationImplementing the State Control Logic with a PLDLatchesState sequence logicREQ1REQ2OPENFLOOR2FLOOR1(16)L1PB(18)L2PB(17)L1PB_(19)L2PB_(12)(13)(14)DOORDIRMOTION(2)(3)(4)(5)(6)(1)(7)CLKARRIVEOE(11)72第73页/共103页 State Control Logic Inputs and OutputsCLK,!OE pin 1,11;REQ1,REQ2 pin 2,3;FLOOR2,FLOOR1,OPEN,ARRIVE pin 4,5,6,7;L1PB,L1PB_ pin 16,17 ISTYPE com,buffer;L2PB,L2PB_ pin 18,19 ISTYPE com,buffer;DOOR,MOTION,DIR pin 12,13,14 ISTYPE reg,buffer;73第74页/共103页State DefinitionsCONSTATE=DOOR,MOTION,DIR;REST1=0,0,0;REST1 =B000;CLOSE1 =B100;UP =B110;REST2 =B001;CLOSE2 =B101;DOWN =B111;74第75页/共103页The Push-Button Latch LogicL1PB=REQ1+(DIR)(OPEN)+(DIR)(FLOOR1)+L1PB_L2PB=REQ2+(DIR)(OPEN)+(DIR)(FLOOR2)+L2PB_L1PB_=(DOOR)(MOTION)(DIR)+L1PBL2PB_=(DOOR)(MOTION)(DIR)+L2PB75第76页/共103页REQ1FLOOR1 DIR DIROPENDOORMOTION DIRL1PBL1PB_(a)Latch for push-button inputs,first floor76第77页/共103页REQ2FLOOR2 DIR DIROPENDOORMOTION DIRL2PBL2PB_(b)Latch for push-button inputs,second floor77第78页/共103页The Boolean equations for the latches are translated into ABEL as follows:L1PB=REQ1#!DIR.FB&OPEN#DIR.FB&FLOOR1#!L1PB_;L1PB_=(!DOOR.FB&!MOTION.FB&!DIR.FB)#!L1PB;L2PB=REQ2#DIR.FB&OPEN#!DIR.FB&FLOOR2#!L2PB_;L2PB_=(!DOOR.FB&!MOTION.FB&DIR.FB)#!L2PB;78第79页/共103页The State Sequence LogicState REST1:if (L2PB)then UP else CLOSE1;State REST2:if (L1PB)then DOWN else CLOSE2;State UP:if (ARRIVE)then REST2 else UP;State DOWN:if (ARRIVE)then REST1 else DOWN;State CLOSE1:if (L2PB)then UP else if L1PB then REST1 else C
