数字集成电路分析与设计 (5).ppt
The CMOS Inverter2The CMOS InvertornVswing=Vdd high noise marginnRatioless logic:Vout does not depend on the device sizes(ratioed logic)nOne transistor always on low output impedance high noise immunitynInput are transistor gates high input impedance,capacitance only infinite steady state fan out(but fan out degrades speed!)nNo steady state DC path from Vdd to ground no static power consumptionKey Points ReviewProperties of Static CMOS invertor3The CMOS InvertornApproach to calculate VMlFirst,assume the working regions of the PMOS and NMOS transistors around VM point,empirically.lThen,equate the currents through PMOS and NMOS to solve for VMlFinally,verify the assumed working regions of the transistors according to the value of VM.If it is not true,repeat the same procedure with a revised working region assumption.nApproaches to calculate noise marginslTraditional approach：according to the definition of noise margin,by differentiate the current equation with respect to Vin lApproximation：piecewise linear approximation approachKey Points Review4The CMOS InvertorKey Points ReviewVinVILSlope=-1VIHSlope=-1VOLVOHVoutHow to get VIH and VIL？Definition of VIH and VILNMH=VOH-VIHNML=VIL-VOL1.Assume the working regions of the NMOS and PMOS,then equate the current flowing through the two transistors：2.Differentiate the current equation(1)with respect to Vin:3.Combine(1),(2),(3)together to derive VIH or VIL，then verify the assumption made at step 1.If it is not true,go back to step 1 and iterates from step 1 to step 3,otherwise proceeding with step 4.(4)4、Obtain noise margins by equation(4)5The CMOS InvertorKey Points Review1.Solve for switching threshold VM2.Solve for the gain g at the switching threshold VM3.Compute VIH and VIL,by the following equation4.Obtain noise margins by the following equationVOLVinV outHow to get VIH and VIL？VMVOHVILVIH=VDD=0A piecewise linear approximation of the VTC simplifies the derivation of VIL and VIH6The CMOS Invertor1.Introduction2.Static Behavior3.Dynamic Behavior4.Power Dissipation5.Summary6.Textbook ReferenceChapter Outline7The CMOS InvertornComputing Load CapacitancenPropagation Delay AnalysisnPerformance Optimization3.Dynamic Behavior8The CMOS Invertor3.Dynamic Behavior:Load CapacitancenPropagation delay of CMOS inverter is determined by the time it takes to charge or discharge the load capacitor CL through the PMOS and NMOS transistorCLnParasitic capacitance CL of the cascaded inverter pairnGate-Drain Cap:Cgd12nDiffusion Cap:Cdb1,Cdb2nGate Cap of Fanout:Cg3,Cg4nWiring Cap:CWVDDVinVout1M1VDDVout2M2M3M4Cdb2Cdb1Cgd12CwCg3Cg49The CMOS Invertor3.Dynamic Behavior:Load Capacitance(Gate-Drain Cap)nGate-Drain capacitance:Cgd12lAssume the input Vin is driven by an ideal voltage source with zero rise and fall timeslM1 and M2 are either in cut-off or saturation mode during the first half of the output transient,therefore only the overlap capacitances deserve to be taken into account.lWhen replacing the gate-drain capacitor by a capacitance to ground,Miller effect should be taken into accountC=Cgd=2CGDOW，CGDO:the overlap capacitance per unit width10The CMOS Invertor3.Dynamic Behavior:Load Capacitance(Diffusion Cap)11The CMOS Invertor3.Dynamic Behavior:Load Capacitance(Gate Cap of Fan-Out)nGate Cap of Fan-Out Cg3 and Cg4 Cfanout=Cgate(NMOS)+Cgate(PMOS)=(CGSOn+CGDOn+WnLnCox)+(CGSOp+CGDOp+WpLpCox)nActual situation is simplified in two ways:lMiller effect on the gate-drain caps are ignored,since the connecting gate does not switch before the 50%point is reached and therefore Vout2 remains constant in the interval of interestlThe channel caps of the connecting gate are constant over the interval of interest.This is a pessimistic and conservative estimation with an error of approximately 10%.12The CMOS Invertor3.Dynamic Behavior:Load Capacitance(Example)Layout of two chained minimum-size inverters(0.25um CMOS)PolysiliconInOutMetal1VDDGNDPMOSNMOS0.25 mm=2l lExample 5.4(P197 in textbook)，how to calculate the lumped capacitances of a 0.25um CMOS inverterExample 5.3(P195 in textbook),how to calculate linearizing factor Keq for a 2.5V CMOS inverter13The CMOS InvertornComputing Load CapacitancenPropagation Delay AnalysisnPerformance Optimization3.Dynamic Behavior14The CMOS Invertor3.Dynamic Behavior:Compute Propagation Delay(Approach One)n Switch ModelRonVDDCLVin=VDDVout15The CMOS Invertor3.Dynamic Behavior:Compute Propagation Delay(Approach One)Simulated transient response of the inverter?tpLHtpHLn Example:(CL,HL=6.1fF,CL,LH=6.0fF)，propagation delay of first inverter00.511.522.5x 10-10-0.500.511.522.53t(sec)Vout(V)tpHLtpLHInput of first inverterOutput of first inverter？1.54.5=2.5VCLRefer to Table 3-3(P106)=39.9p=31.7p16The CMOS Invertor3.Dynamic Behavior:Compute Propagation Delay(Approach Two)n Current sourceVDDVoutVin=VDDCLIav17The CMOS Invertor3.Dynamic Behavior:Analysis of Propagation Delayn Expression of propagation tpHL=0.69neglectednIf VDD VTn+VDSATn/2l Under the above condition,the delay is virtually independent of the supply voltagel Due to the impact of channel-length modulation,increasing the supply voltage yields a small improvements in performance(i.e.reduction of the delay)18The CMOS Invertor3.Dynamic Behavior:Analysis of Propagation Delay0.811.21.41.61.822.22.411.522.533.544.555.5VDD(V)tp(normalized)Propagation Delay as a function of Supply Voltage nIncreasing the supply voltage above a certain level yields only very minimal reduction of tp,due to the channel length modulation effect.nWhen supply voltage is low,the predicted value of tp deviates from the simulated one,because the devices are not velocity saturated any more.nWhen the supply voltage is around 2VT,a sharp increase of tp can be detected.Should be avoided definitely.Predicted(first order approximation)Please compare with Figure 3-28 in textbook(P106),introduced in Lecture Two19The CMOS InvertornComputing Load CapacitancenPropagation Delay AnalysisnPerformance Optimization3.Dynamic Behavior20The CMOS Invertor3.Dynamic Behavior:Analysis of Propagation DelaynDesign Techniques of Performance OptimizationlReduce CLInternal diffusion capacitance(diffusion areas should be as small as possible)Interconnect capacitancesFanout capacitancelIncrease the W/L ratio of the transistorPros.:enhancing the driving strength(increasing(dis)charging currents as well as decreasing on-resistance of the transistor）Cons.：raising the diffusion capacitance and hence CL(Self-loading),increasing the fan-out of the driving gatelIncrease VDDVery high supply voltage has a very minor impact on delay reductionPower consumption is increased,accordingly.Firm upper bounds should be abided due to the reliability concernsDepends on layout design21The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case One)nCase one：A symmetrical inverter(tpHL=tpLH)is illustrated in the right figure,solve for the relation between propagation delay tp and the sizing factor S(which relates the size of this inverter to a reference minimum-sized inverter)n Load cap.CL consists of two components CL=Cint+Cext Cint：intrinsic(self-loading)cap.,attributable to diffusion and gate-drain overlap caps.Cext：extrinsic load cap.,attributable to fan-out and wiring caps.n Propagation Delay tp：tp=0.69Req(Cint+Cext)=0.69ReqCint(1+Cext/Cint)=tp0(1+Cext/Cint)tp0：intrinsic or unloaded delay（delay of the inverter only loaded by Cint)22The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case One)n A minimum-sized reference inverter serves as a reference gate,whose intrinsic cap.equals Ciref，and on-resistance equals Rrefl Intrinsic cap.of the inverter with a sizing factor S(W/L of the two transistors are both scaled with a factor of S with respect to the minimum-sized one)is therefore equal to SCiref,and its corresponding on-resistance is equal to Rref/S tp=0.69(Rref/S)(SCiref)(1+Cext/(SCiref)=0.69RrefCiref(1+Cext/(SCiref)=tp0(1+Cext/(SCiref)nThree important conclusions can be drawnlThe intrinsic delay of the inverter tp0 is independent of the sizing of the gate,and is determined purely by technology and inverter layout.If the sizing factor S is increased,the on-resistance is decreased accordingly,however suffered from the penalty of the increased intrinsic capacitance.lIf Cext=0,increasing the gate size no longer helps in reducing the delay,because increase in the drive of the gate is totally offset by the increased cap.lIf Cext!=0,making S infinitely large yields the maximum obtainable performance gain,reducing the delay to the intrinsic one(tp tp0).If S is sufficiently larger than Cext/Cint,any further increase of the sizing factor S helps little in reducing the delay(self-loading effect),however the gate area will be tremendously enlarged(see next foil)23The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case One)Self-loading effect:Intrinsic capacitances dominate(for fixed load)Increasing inverter performance by sizing the NMOS and PMOS transistor with an identical factor S for a fixed fan-out lIf Cext!=0,making S infinitely large yields the maximum obtainable performance gain,reducing the delay to the intrinsic one(tp tp0).If S is sufficiently larger than Cext/Cint,any further increase of the sizing factor S helps little in reducing the delay(self-loading effect),however the gate area will be tremendously enlarged.24The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Two)nCase Two：Consider two identical cascaded CMOS inverters,to derive the expression relating tp (propagation delay of the first inverter)to (=(W/L)p/(W/L)n )l Assume the on-resistance of the NMOS transistor in right figure is Reqn,and that of the PMOS,who has the same size as this NMOS transistor,is Reqp.Therefore the on-resistance of the PMOS transistor(who is scaled times)in right figure,is equal to Reqp/l If the equivalent high-to-low and low-to-high propagation delays are required,i.e.tpHL=tpLH,should be equal to Reqp/Reqn.l To minimize propagation delay tp of the first inverter,CL,Req,tp can be expressed as:25The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Two)nPropagation Delay tp：lIn order to minimize tp,the optimal value of can be found26The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Two)11.522.533.544.5533.544.55x 10-11btp(sec)Propagation delay of CMOS inverter as a function of PMOS-to-NMOS transistor ratio tpLHtpHLtp=(W/L)p/(W/L)n Minimum Propagation Delay 1 1.9 Symmetrical transient response (tpLH=tpHL)2 31K/13 K 2.4 Refer to Table 3-3(P106)in Textbookb b1b b2Smaller device sizes(and thus a smaller design area)yield a faster design at the expense of symmetry and noise margins!27The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)CLlGiven CL：lHow to choose the number of stages so as to minimize the delay?lHow to determine the sizing of the inverters?InOutnCase Three:Sizing a Chain of InverterslHow to drive a large load capacitance CLlSimplification of the real situation28The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)n Assume the input gate Cap.and the output intrinsic Cap.of the inverter have the following relationship:where,is a proportionality factor that is only a function of technology(1 for most submicron process)Where,tp0 represents the delay of the inverter only loaded by its own intrinsic Caps.,which is called the intrinsic or unloaded delay and independent of the sizing of the gatenAssume Cext=f Cg，where f=Cext/Cg,which is called the effective fan-outThe delay of an inverter is only a function of the ratio between its extrinsic load Cap.and its input Cap.=29The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)n Apply the propagation delay equation to the inverter chainCLInOut12Nl Total delay through the inverter chain:tp=tp,1+tp,2+tp,N (1)30The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)nScenario One of inverter chain problem:given stage number N to derive the optimum effective fan-out f31The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)F represents the overall effective fan-out of the circuit.32The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)CL=8 C1InOutC11ff 2l C CL L/C C1 1 should be amortized over should be amortized over N N(=3)stages,therefore:(=3)stages,therefore:nExample of scenario one:assume Example of scenario one:assume N N=3,solve for the effective fan-out=3,solve for the effective fan-out f f？How to choose the number of stages so that the delay is minimized for a given value of How to choose the number of stages so that the delay is minimized for a given value of F F,which is much more similar to the real casewhich is much more similar to the real case？33The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)n Scenario Two of inverter chain problem：for a given load cap.CL and input gate Cap.Cin,solve for the optimum value of the effective fan-out f and stage number NlIn right equation,if N is too large(f is therefore small),the first component becomes dominant,otherwise,the second component dominateslTo derive the minimum delay,tp is expressed as the function of F,f and Where34The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)n If =0(no self-loading)，according to the equation l thus：fopt =e=2.71828,N =ln FNo self-loading35The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Case Three)Optimum effective fan-out f as a function of the self-loading factor Normalized propagation delay(tp/tp,opt)as a function of the effective fan-out for =1Choosing values of the effective fan-out that are a little bit higher than the optimum reduces the required number of stages as well as implementation area,but not affecting the delay very much.Normally,the optimum fan-out is selected to be 4.The use of too many stages (f tpHL:linear relationnKeeping the input transition time of the gate less than its propagation delay is definitely beneficial to performance increase as well as power reduction Calculation can be located at Example 5.9，P212 in textbook42The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Impact of Input slope)3-Input NAND cell (from ST Microelectronics):C=Load capacitance,T=input rise/fall time43The CMOS Invertor3.Dynamic Behavior:Performance Opt.(Problem Five)nProblem FivelDetermine if reducing the supply voltage increases or decreases the influence of the input signal slope on the propagation delay.Explain your answer44The CMOS Invertor3.Dynamic Behavior:SummarynCalculation of load capacitancelIntrinsic Cap.(Gate-Drain Cap.and drain diffusion Cap.)lExtrinsic Cap.(Gate Cap of Fan-out and wiring Cap.)nPropagation Delayl0.69ReqCLlCL(Vswing/2)/IavnDesign of Performance OptimizationlA single inverter driving a fixed load Cap.(Case One)lA single inverter driving another identical inverter(Case Two)lSizing a chain of inverter(Case Three)Given F and N(Scenario One),derive fGiven F only(Scenario Two),derive f and N45The CMOS Invertor1.Introduction2.Static Behavior3.Dynamic Behavior4.Power Dissipation5.Summary6.Textbook ReferenceChapter Outline46The CMOS Invertor4.Power Dissipati
