第四讲 补充.ppt

Flexible Architectures for Wideband SDR ChannelisationSteve MatthewsRF Engines LimitedRF Engines Established-1999 Location-Isle of Wight,UKFPGA based Signal Processing for Defence,Communications and Instrumentation ApplicationsChannelisation“Processing a wide bandwidth of radio spectrum to produce narrower channel(s)”Channeliser (Downconverter)(Filter Bank)Wideband Input Signal 1 2 3 N Narrowband Outputs 1 3 N 2.RF Engines ChannelisersDigital channelisation techniquesVery wideband inputsMultiple channelsFlexibilityThe Need For Flexibility25MHz824MHz849MHzGSM:125 x 200kHzCDMA2000:10 x 1.25 MHzIS136:833 x 30kHzAn Example:800 MHz Telecoms BandFlexibilityControllable channel filter shapesTuneable channel centre frequenciesSelectable output sample ratesIndependent channelsSuitability of Different Channeliser ArchitecturesChannelisation ArchitecturesDigital Downconverter(DDC)Fixed Multichannel DownconvertersWindowed FFTWOLA(Polyphase DFT)Mixed Radix FFTFlexible Multichannel DownconvertersPipelined Frequency Transform(PFT)Tuneable Pipelined Frequency Transform(TPFT)Channelisation ArchitecturesDigital Downconverter(DDC)Fixed Multichannel DownconvertersWindowed FFTWOLA(Polyphase DFT)Mixed Radix FFTFlexible Multichannel DownconvertersPipelined Frequency Transform(PFT)Tuneable Pipelined Frequency Transform(TPFT)Digital Down-converters(DDC)Wideband Input Signal-Fs/2+Fs/2NCO频率率变换复信号输入复信号输入LPF低通低通滤波波D抽抽值复信号输出复信号输出Shifted Signal-Fs/2+Fs/20HzSpectral ShiftDecimated Signal-Fs/2N+Fs/2NFiltered Signal-Fs/2+Fs/20HzDigital Down-converters(DDC)B+CD-ALow PassFilters(CIC/FIR)IQIQLocal OscillatorFrequency=FLOCosineSineDCBA6464DecimatorsDecimating FIRCIC Filter used in DDCG=1/RNI积分分I积分分I积分分 32C微分微分C微分微分C微分微分输入采样率=122.88MHz Fs(complex)输出采样率=1.96Mhz Fs/R(complex)Z-1 Z-M-1Sub-sampleDDC Filter Performance-1000-20-40-60-80dB0-Fs/2+Fs/2FrequencyInput Bandwidth +Fs/2Input Sample Rate(S/R)=Fs(Complex)Output Bandwidth +Fs/2NOutput S/R=Fs/N(Complex)Multiple DDC Performance0-20-40-60-80-100dB0-Fs/2+Fs/2FrequencyIndividual Filters can be Tuned for Bandwidth,Centre Frequency and Filter ShapeMulti-channel DDC Architecture16选频DDC SummaryChannelisation ArchitecturesDigital Downconverter(DDC)Fixed Multichannel DownconvertersWindowed FFTWOLA(Polyphase DFT)Mixed Radix FFTFlexible Multichannel DownconvertersPipelined Frequency Transform(PFT)Tuneable Pipelined Frequency Transform(TPFT)FFT Based ChannelisationFFTN time-domain samplesN frequency-domain bins“N Channels regularly spaced at Fs/N”Each bin is a filtered,down-converted and decimated channelChannel Spacing Controlled by sample rate and transform sizeChannel Sample Rate Fs/N,or controlled by overlapping FFTsFilter Shape sinc/x function for non-windowed FFT,or controlled by Window functionExample GSM ChanneliserComplex Sample Rate(Fs)=Input Bandwidth=102.4 MHzFFT Size(N)=Number of channels=512Channel Spacing=200 kHzChannel Sample Rate=200 kHzFilter performance for Windowed FFTKaiser Windowed 32-point FFT0-20-40-60-80-100dB0-Fs/2+Fs/2FrequencyChannel Spacing=Fs/NWeight,Overlap and Add(WOLA)xnWeight data by weighting functionhninput dataDsamplesat a timeDivide into blocks of K samplesoverlapandaddK-point FFTXPhase correction+weighting functionInput Sample Rate=FsChannel Spacing=Fs/KChannel Sample Rate=Fs/DOver-sampling Rate =K/DPolyphase DFT A special case of WOLA with integer over-sampling rateHigh Performance Filter BankLWOLA Filter PerformanceN=32-points0-20-40-60-80-100dB0-Fs/2FrequencyChannel Spacing=Fs/NSuperior Cut-Off&Stop-Band Performance+Fs/2WOLA Examplexnhninput dataD=256samplesat a timeoverlapandadd512-point FFTXPhase correction+weighting functionGSM ExampleL=2048D=256K=512Channel Spacing=200 kHzChannel Sample Rate=400 kHz2 x Over-sampled256256256256256256256256512512512512L=2048Sample rate is NOT a multiple of the GSM symbol rate!Mixed-Radix FFTUse of mixed-radix FFTs allows arbitrary length DFTs to be builtGreater flexibility for channel spacing and sample ratesInteger values for K and D must be found to satisfy:K/D=fdemod/fExample GSM ChanneliserChannel Spacing=200kHz Symbol Rate=270.833 kHzTo achieve a sample rate at exactly twice the symbol rate one solution is:Fs=52MHz D=96 K=260This requires a 260-point DFT!This example is being targeted at Virtex-II 6000 device to produce a 200-channel GSM channeliser.FFT SummaryChannelisation ArchitecturesDigital Downconverter(DDC)Fixed Multichannel DownconverterWindowed FFTWOLA(Polyphase DFT)Mixed Radix FFTFlexible Multichannel DownconverterPipelined Frequency Transform(PFT)Tuneable Pipelined Frequency Transform(TPFT)Pipelined Frequency TransformPatented multi-resolution frequency transform techniqueBased on a binary band-splitting principleInputFilter Bank A OutputFilter Bank B OutputFilter Bank C Output0Hz0Hz0Hz0Hz0Hz0Hz0Hz-Fs/2+Fs/2-Fs/4+Fs/4Etc.PFT Basic Tree SystemSampleRate=Fs/4Input SampleRate=FsSampleRate=Fs SampleRate=Fs/2CUC(C)CDC(C)CDC(B)IQCUC(C)CDC(C)CDC(B)IQCUC(C)CDC(C)CUC(B)IQCUC(C)CDC(C)CUC(B)IQCDC(A)CUC(A)IQQIIQCDC=Complex Down-ConverterFor N=10,PFT Bins=1024,No.Modules=2046!CUC=Complex Up-ConverterPFT Interleaved SystemTotal No.of CDC/CUC Modules=2*Log2(N)For N=10,PFT Bins=1024,No.Modules=20 ICUC(C)ICDC(C)IQIIQQICUC(B)ICDC(B)IQIIQQIQCUC(A)CDC(A)IIQQQIInput Sample rate=Fs1:2 Sample Interleavers Output Sample Rate=2Fs2:4 Sample Interleavers/Decimators Output Sample Rate=2Fs4:8 Sample Interleavers/Decimators Output Sample Rate=2FsEtc.PFT General CDC/CUC ArchitectureOutput Sample Rate=Fs/N(Complex)Output Bandwidth +/-Fs/2NInput Sample Rate=Fs(Complex)Input Bandwidth +Fs/2B+CD-ALow PassFIR FiltersIQIQLocal OscillatorFrequency=FLOCosineSineDCBANNDecimatorsPFT Simplified CDC ArchitectureIQI OddI EvenQ OddQ EvenSample InterleaversInput Sample Rate=Fs/2 Input Bandwidth=+/-Fs/21,1,-1,-1,.1,-1,-1,1,.Low Pass Filter 0-Fs/4Simplified LocalOscillators&MultipliersAux O/PAux O/PAux O/P2 Points4 Points8 PointsN PointsPFT Simultaneous OutputsSimultaneous outputs of PFT stages with different number of bins and resolution bandwidths.For example,a 256 point PFT with 400 kHz RBW at same time as 16K point PFT with 6.25 kHz RBWUseful for catching fleeting signal in the wider RBW with faster update time.PFT vs Polyphase DFTBoth support regularly spaced channelisation,with high quality filteringPFT Featuresmulti-resolution outputsmultiplier-less designSilicon efficiency roughly the same up to 256-channelsFor greater number of channels Polyphase DFT gains rapidlyButPFT has important uses in a tuneable architectureAllows multiple signals with different bandwidth to be extracted from the digitised input spectrumUser selects centre frequency,bandwidth and filter shape to be used for the extractionRouting algorithm works out best configuration for the PFTTPFT can be dynamically re-configured to meet changing requirements by re-routingTuneable PFT(TPFT)Tuneable PFT(TPFT)InterleaverCDC/CUCFine-TuningCoarse tuning by PFT stagesFine tuning Final shaping filter to match bandwidth and shapePFT stage 1PFT stage 2PFT stage 3PFT stage NFine Tune&FilterStage 3Stage 1Stage 2Choice of PathsTPFT Routing AlgorithmTPFT with a 5-Stage PFT0-20-40-60-80-100dB0-Fs/2+Fs/2FrequencyIndividual Filters can be Tuned for Bandwidth,Centre Frequency and Filter ShapeTPFT ExampleExample Tuneable ChannelisersSummary of Channeliser TechniquesSummary of Channeliser TechniquesTPFTSimilar flexibility to DDCMore efficient for more than 8 channelsOptimisations for specific scenariosSample Rate FlexibilityAll basic channelisation techniques have limited output sample rate flexibilityRate ChangeDown-sample or Up-sampleN input channels with independent sample ratesN output channels with independent sample ratesResample by I/MIndependent for each channelRF Engines Interleaved Fractional Re-sampler CoreParameterisableNumber of channelsMinimum decimationDecimation filter performanceBit widthsExample Flexible Resampler CoreFlexible Downsampler CoreInputMax 512 channelsMax channel rate:25 MHzMax aggregate rate:180MHz18-bit integersRate Change by I/236I programmable at run-time Milli-Hertz rate resolutionMinimum rate change:0.01InterleaveOutput36-bit integersSilicon Requirements for Xilinx Virtex II Pro 50Logic:12%Multipliers:7%Block RAMs:16%Example Flexible Channeliser Core with ResamplerChannelCore642 input channels up to 140 MS/s16-bit64 independent output channels ChannelCore64 64 Channel Flexible DownconverterFeatures:Full channel independenceTune channels to 0.01 Hz resolutionFully selectable bandwidths/decimation rates.(Max bandwidth 450kHz)Four programmable channel filter shapesFractional resampler set output rates with 0.01Hz resolution.Replacement for ASIC based DDCsFits within Xilinx Virtex II Pro 30SummaryDDC architecturesVery flexible.Good for small numbers of channelsFixed Multichannel DownconvertersVery efficient for large numbers of regular spaced channelsUse WOLA/Polyphase DFT for high quality filtersUse Mixed-Radix FFT for sample rate Flexible Multichannel DownconvertersPFT,multi-resolution filter bankTPFT,efficient and flexible approach to multi-channel channelisationFlexible ResamplerApplicable to all architectures for obtaining precise sample rates rfengines limited