OMAP3530技术参考手册.docx

一、启动1、x-loader 是一级引导程序，系统上电后由CPU 内部 firmware 自动拷贝到内部RAM 并执行。主要作用为初始化CPU，拷贝u-boot 到内存中，然后把把握权交给u-boot；2、u-boot 是二级引导程序，主要用于和用户进展交互，供给映像更、引导内核等功能；3、kernel 使用最 2.6.32 内核，依据SOC8200 进展定制；4、rootfs 承受开源文件系统，体积小，功能强大。温馨提示：J24 接上跳线帽后，上电启动的时候，系统将会优先从 SD 卡启动。更NANDFLASH：更 NAND Flash 需要在 u-boot 的命令行上对 NAND 操作，系统从 SD 卡启动后通过U-boot 烧写NANDFLASH。第 1 章 Introduction1.1 疑问：1） OMAP35x OneDRAM 技术具体是指？ POP 封装顾名思义, 是两个芯片叠在一起对于 OMAP3 的 POP 封装, OMAP3 外表供给焊盘, mDDR 贴在 OMAP3 的外表, Beagle板子就是这样的, 这样的好处是省去了PCB 面积和DDR 的走线, 害处是生产比较困难2） OMAP35x 仅有 6 个GPIO，而AM3517 有 186 个GPIO？解决：A maximum of 170 GPIO pins are supported. The following GPIO pins are not available: gpio_52, gpio_53, gpio_63 gpio_64, gpio_144, gpio_145, gpio_146, gpio_147, gpio_152, gpio_153, gpio_154, gpio_155, gpio_175, and gpio_176. Pin muxing restricts the total number of GPIO pins available at one time. See your device-specific data manual for more information on pin multiplexing.3） VA2.2 subsystem (DSP) cant access SoC peripherals。存在质疑，网上说可以4） Chip select pins mcspi1_cs1 and mcspi_cs2 are not available on the CUS package. 5High-speed USB host controller port 3 is not available on the CUS package1.2 未用模块的建议：General Recommendations Relative to Unavailable Features/ModulesAs explained in the previous section, some features are not available in all OMAP35x devices. For unavailable features, use the following recommendations: Memory mapping: Memory area of unavailable modules and features are RESERVED, read isundefined, and write can lead to unpredictable behavior. Interrupt controllers: Ensure that interrupts of unavailable modules and features are masked in MPU/IVA subsystems. DMA: Ensure that DMA requests of unavailable modules and features are masked in DMA subsystems. System Control Module (SCM): Unavailable modules and feature pins are not functional and should not be used. Power, Reset, and Clock Management Module (PRCM): For power management and power-saving consideration, ensure that power domains of unavailable features/modules are switched off and clocks are cut off. Interconnect: To flag potential interconnect outstanding commands, the time-out of target agents attached to unavailable modules can be enabled with the lowest setting.第 2 章 Memory Mapping存储空间图见OMAP35x 技术参考手册.pdf199 页2.1 地址空间Boot spaceThe system has a 1MB boot space in the on-chip boot ROM or on the GPMC memory space. When booting from the on-chip ROM with the appropriate external sys_boot5 pin configuration, the 1MB memory space is redirected to the on-chip boot ROM memory address space 0x4000 0000 0x400F FFFF. When booting from the GPMC with the appropriate external sys_boot5 pin configuration, the memory space is part of the GPMC memory space.SDRC spaceTwo SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available on the third quarter (Q2) of the addressing space to access SDRAM memories. The chip-selects have a programmable size (64, 128, 256 or 512MB) in a total memory space of 1GB.The base address of the chip-select 0 (sdrc_ncs0) memory space is always0x8000 0000. The base address of the chip-select 1 (sdrc_ncs1) memory space is programmable. The default value after reset is 0xA000 0000.VRFB spaceThe SDRC-SMS virtual memory space is a different memory space used to access a subset of the SDRC memory space through the rotation engine. The virtual address space size is 768MB split into two parts: The first 256MB part is in the second quarter (Q1) of the memory; the second 512MB part is in the fourth quarter (Q3) of the memory.L3 处理存储器数据交换，L4 处理外设之间的交互。L1 and L2 are memories in in the MPU and the IVA2.2 subsystems.The chip-level interconnect, which consists of one L3 and four L4s, enables communication among all modules and subsystems。Accesses to the L3 interconnect can be configured on a per-module basis using the internal L3registersThis section describes how the IVA2.2 internal memories and registers are accessed through the L3 interconnect and by the IV A2.2 internal initiators (the digital signal processor DSP and the enhanced direct memory access EDMA).DSP 局部内存：C64x+ DSP program memory controller 配置 L1P，L1D，L2 作为RAM 或者Cache 使用。当L1 部安排置为 cache 时，对于 DSP 访问 L2 可以起到加速的作用。DSP 访问的存储器和外设是基于虚拟地址的。The IVA2.2 subsystem contains 16KB of L2 ROM. The L2 ROM providesboot codeDSP and EDMA access the memories and peripherals using virtual addressing. This lets the DSP and EDMA access memories and peripherals in the same contiguous view, even when the memory is physically segmented。The IVA2.2 memory management unit (IVA2.2 iMMU) handles the virtual-to-physical addresstranslation based on the software configuration (typically under control of the MPU subsystem).注：MPU 把握iMMU 进展虚拟地址到物理地址的转换。IVA2.2 internal memories are reachable in the 0x007E 0000-0x00F1 7FFF and 0x107E 0000-0x10F1 7FFF (aliasing) ranges第 3 章 MPU Subsystem3.1 概述MPU 子系统治理ARM 内核，L3，INTC。第 7 章 System Control ModuleSCM 可以进展配置的特性：见：SCM Register Manual，860 页1） 空闲模式参数设置2） MCBSP 参数配置3） DMA 的触发模式4） control the use of MSuspend signals at module levelMPU、DSP 5 camera 设置6） 把握DSS，PER，CORE 等 EMI 削减措施7） SDRC 配置8） 防火墙写许可配置9） MMC 电压把握10） 可观测性配置Observability is disabled. If pads are configured for the”hardware debug”, output is tied low SCM 仅对开机复位响应。PRCM 可以把握SCM 进入休眠模式。The SCM does not generate interrupt or wake-up requests。The SCM responds only to the internal power-on reset and to the device type. At power-on, reset values for the registers define the safe state for the device. In the initialization mode, only modules used at boot time are associated with the pads. Other module inputs are internally tied, and outputs pads are turned off each time the feature is available。注：启动期间使用模块和pad 有关，未用模块输入被约束，输出关闭。After power-on reset, the software sets the pad functional multiplexing and configuration registers to the requested device pad configurations. Data written in these registers command directly the multiplexing of the pad configuration logic.注：通过存放器的配置直接把握引脚复用。Each pin is configurable by software using its associated pad configuration register field, which is 16 bits wide MUXMODE (3 bits) defines the multiplexing mode applied to the pin. A mode corresponds to the selection of the functionality mapped on the pin with six (0 to 5) possible functional modes for each pin. PULL (2 bits) for combinational pullup/pulldown configuration: PULLTYPESELECT: Pullup/pulldown selection for the pin. PULLUDENABLE: Pullup/pulldown enable for the pin. INPUTENABLE (1 bit) drives an input enable signal to the I/O CTRL. INPUTENABLE = 0: Input Disable. Pin is configured in output only mode. INPUTENABLE = 1: Input Enable. Pin is configured in bidirectional mode. Off mode values (5 bits) override the pin state when the OFFENABLE bit CONTROL. CONTROL_PADCONF_X is set and off mode is active. This feature allows having separate configurations for the pins when in off mode: OFFENABLE: Off mode pin state override control. Set to 1 to enable the feature and to 0 to disable it. OFFOUTENABLE: Off mode output enable value. Set to 0 to enable the feature and to 1 to disable it. OFFOUTVALUE: Off mode output value. OFFPULLUDENABLE: Off mode pullup/pulldown enable OFFPULLTYPESELECT: Off mode pullup/pulldown selection注：The OFFOUTENABLE and OFFOUTVALUE bits are functional only if the pad configuration supports output mode on at least one MUXMODE. For a pad that supports only the input feature, the OFFOUTENABLE and OFFOUTVALUE bits cannot be configured (they are don”t care and read always returns 0) Wake-up bits (2 bits): WAKEUPENABLE: Enable wake-up detection on input. It is also the off mode input enable value. WAKEUPEVENT: Wake-up event status for the pin注：The software must configure the OFF mode pads. It must ensure that the input/output capability is enabled for each pin。注：Functional modes are defined from 0b000 to 0b101; mode 0b111 is referred to as the safe mode. 模式 0-模式 5 为功能模式，模式 7 为安全模式。通常复位状态为安全模式。 The exceptions are pads to be used at boot time to transfer data from selected peripherals to the external flash memory模式 0 为初始模式，当配置为模式 0 时，功能与引脚名一样。The safe mode avoids any risk of electrical contention by configuring the pin as an input with no functional interface mapped to it. The safe mode is used mainly as the default mode for all pins containing no mandatory interface at the release of power-on reset.上下拉：当引脚配置为输出时，引脚的上下拉自动关闭。引脚复用见：OMAP35x 技术参考手册.pdf772 页The D2D pads are available in stacked mode only.系统关闭模式：Whenoffmodeisactive(PAD_SYS_OFF_MODE=0b1fromPRCMor FORCEOFFMODEENABLE bit CONTROL.CONTROL_PADCONF_OFF0 = 0b1), the offmodevaluesfieldCONTROL.CONTROL_PADCONF_X overridesthepadstatewhen OFFENABLE bit CONTROL. CONTROL_PADCONF_X is setIf off mode is active and the OFFENABLE bit is set to disable, the pad keeps the AND value of the configuration (input/output, PU/PD) it had before going into off mode: For an input, the pad is isolated and the pull remains active. For an output, the value is latched before going into off mode, to drive the same value in off mode唤醒机制：When wake-up detection is enabled for a pad, the pad must be configured as input to avoid contention between the OMAP output buffer and an external driver.If this pin is configured as an output in active mode, the OFF override function must be enabled to set the pin as an input during off mode: in the CONTROL.CONTROL_PADCONF register, set OFFENABLE to 0x1 to enable the OFF override function, and set OFFOUTENABLE to 0x1 to switch this pin to input mode.PBIASLITEPWRDNZ0/PBIASLITEPWRDNZ1signalto0b0wheneverthe MMC1_VDDS/SIM_VDDS signal is ramping. When this bit is at 0, the PAD is floating。With the appropriate configuration of the PBIAS cell, gpio120 through gpio129 I/Os(MuxMode =0x4) can operate in 3-V mode.OMAP 内部有一个基于ADC 的温度传感器。可以检测温度值。注：Use care when using combined sensitivity settings (ANDing or ORing DSP and MPU MSuspend signals).ORing the DSP and MPU MSuspend signals creates a situation where the module is suspended when at least one processor is under debug; therefore, when one processor is halted, stepping within the code of the other one does not change the module suspended state.Not all modules use the MSUSPEND signal. See the TRM chapter for each module to determine whether the module supports the MSUSPEND signal.All MSUSPEND signals coming out of the MPU and DSP are resynchronized within the SCM by using the control module interface clockDSP 启动地址和启动模式存放器调试引脚配置：The pads used for the hardware debug must be properly configured by selecting the hardware debug function (hw_dbgn) of the pad. To configure the pads, select mode 5 (0b101) in the MUXMODE bit field of the CONTROL.CONTROL_PADCONF_CAM_x register (only for hw_dbg0 to hw_dbg11), or select mode 7 (0b111) in the MUXMODE bit field of the CONTROL.CONTROL_PADCONF_ETK_x register (for all hw_dbgn). Before selecting the CORE signals, the WKUPOBSMUX bit field of theCONTROL.CONTROL_WKUP_DEBOBS_n registers must be set to 0.可观测性：To disable observability for all hw_dbg I/Os (that is, drive the external observability outputs to 0), observability of the CORE and WKUP domains must be disabled. Disabling only wkup_observability is not sufficientEMI：内部的频率修调机制可以削减电源尖峰，The SCM contains all necessary bits that controls the EMI reduction feature (SSC)，In any case, the frequency modulation is programmed in the SCM and does not generally need to be changed in real time.设备内部抗干扰措施：The spreading technique “scatters“ the energy of the peaks on the other frequencies, which reduces the power of the peaks but increases the global “noise“ of the signal.电源芯片：If the device is associated with the companion power IC, before using the MMC/SD/SDIO1 interface, the software must program the companion power IC toenable the VMMC1 or VSIM (for the MMC/SD/SDIO1 module or muxed GPIO I/Os) and the LDO and to provide a 1.8-V/3.0-V voltage. This is done by software through the I2C interface that links the device and companion power ICIf the application does not want the selected interface running at 3.0 V, software users must then assert the VMODE signal to low for 1.8-V activity: in this case, the PBIAS is connected to ground.If MMC1_VDDS (or SIM_VDDS) is supplied before the device reset is released, the voltage must be 3 V. It is not recommended to supply the vdds_mmc1 (or vdds_sim) pad with 1.8 V unless software has configured the PBIAS cells accordingly.A PBIAS cell must be programmed according to peripheral power supply voltagethe programming flow to go from 3.0 V to 1.8 V, and vice versa The following are critical requirements for the cell: The VMODE bit must be defined before the PWRNDZ bit is made HIGH(cell is brought out ofPWRNDZ). The default state of VMODE bit must be HIGH (to indicate 3.0-V operation). PWRNDZ bit must be kept LOW when the MMC1_VDDS/SIM_VDDS supply is ramping up (PWRNDZ bit is not required to be kept LOW during ramp down of the supply). This could be damaging.Off Mode Preliminary SettingsThe following actions must be performed once, and remain valid for all device OFF <-> ON transitions: Program a valid device OFF pads configuration, by setting in each CONTROL.CONTROL_PADCONF_X registers all off mode values bits: OFFPULLTYPESELECT (OFF mode pull type), OFFPULLUDENABLE (OFF mode pull enabling), OFFOUTVALUE (OFF mode output value),OFFOUTENABLE (OFF mode output enabling), OFFENABLE (OFF mode pad state override control) . Program a valid device ACTIVE pads configuration by setting pertinent bits in eachCONTROL.CONTROL_PADCONF_Xregister(seeSection7.5.4,PadConfiguration Programming Points). Perform a device ACTIVE pads configuration saving in the save and restore memory fromWake-upControlModulebyassertingtheSTARTSAVEbit CONTROL.CONTROL_PADCONF_OFF1. Set the SCM in smart idle mode by setting the IDLEMODE fieldCONTROL.CONTROL_SYSCONFIG4:3 (this will ensure that its clocks can not be cut until the save procedure has completed). Enable/disablethewakup-upeventdetectioncapabilityofthepadsbysettingtheWAKEUPENABLE bit CONTROL. CONTROL_PADCONF_X.注：When the wake-up detection is enabled for a pad, this pad is configured as input. Therefore, do not forget to write 0b1 in the OFFOUTENABLE bit CONTROL. CONTROL_PADCONF_X to disable the output capability复用引脚配置要点： Identify signals required on the interface based on the target application. 1确定系统需要使用哪些信号；Example: To configure the UART1 interface on balls, the required signals are uart1_tx, uart1_rts,uart1_cts, and uart1_rx. Choose the pads used for those signals. Some signals could be available on several pads and/ormay be multiplexed with other signals needed for another application. See Section 7.