函数信号发生器课程设计报告.docx

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1、函数信号发生器课程设计报告函数信号发生器课程设计报告 本文关键词：函数，课程设计，信号发生器，报告函数信号发生器课程设计报告 本文简介：课程设计报告书专用纸淮海工学院课程设计报告书课程名称：电子技术课程设计题目：函数信号发生器学院：电子工程学院学期：2022-2022-2专业班级：通信工程111姓名：彭孟瑶学号：2022120688评语：成果：签名：日期：函数信号发生器1.引言在人们相识自然、改造自然的过程中，常常须要对各种各样的电函数信号发生器课程设计报告 本文内容：课程设计报告书专用纸淮海工学院课程设计报告书课程名称：电子技术课程设计题目：函数信号发生器学院：电子工程学院学期：2022-2

2、022-2专业班级：通信工程111姓名：彭孟瑶学号：2022120688评语：成果：签名：日期：函数信号发生器1.引言在人们相识自然、改造自然的过程中，常常须要对各种各样的电子信号进行测量，因而如何依据被测量电子信号的不同特征和测量要求，敏捷、快速的被测电路供应所须要的已知信号(各种波形)，然后用其它仪表测量感爱好的参数。可见信号源在各种试验应用和试验测试处理中，它不是测量仪器，而是依据运用者的要求，作为激励源，仿真各种测试信号，供应给被测电路，以满意测量须要。波形发生器就是信号源的一种，能够给被测电路供应所须要的波形，传统的波形发生器多采纳模拟电子技术，由分立元件或模拟集成电路构成，其电路结

3、构困难，不能依据实际须要敏捷扩展。随着微电子技术的发展，运用单片机技术，通过奇妙的软件设计和简易的硬件电路，产生数字式的正弦波、方波、三角波、锯齿等幅值可调的信号。与现有各类型波形发生器比较而言，产生的数字信号干扰小，输出稳定，牢靠性高，特殊是操作简洁便利。2.设计要求设计一个能够输出正弦波、三角波和矩形波的信号源电路，电路形式自行选择。输出信号的频率可通过开关进行设定，详细要求如下：输出信号的频率范围为10002000Hz，步进为50Hz。要求输出信号无明显失真，特殊是正弦波信号。图1函数信号发生器方框图3.函数信号发生器的方案3.1方案一由555定时器组成的多谐振荡器产生方波，然后由积分电

4、路将方波转化为三角波，最终用低通滤波器将方波转化为正弦波。低通滤波器积分电路555多谐振荡器图2方波、三角波、正弦波、信号发生器的原理框图但这样的输出将造成负载的输出正弦波波形变形，因为负载的变动将拉动波形的崎变。3.2方案二先通过RC正弦波振荡电路产生正弦波，再通过电压比较器产生方波，最终通过积分电路形成三角波。积分电路电压比较器RC正弦波振荡电路图3正弦波、方波、三角波信号发生器的原理框图此电路具有良好的正弦波和方波信号。但经过积分器电路产生的同步三角波信号，存在难度。缘由是积分器电路的积分时间常数是不变的，而随着方波信号频率的变更，积分电路输出的三角波幅度同时变更。若要保持三角波幅度不变

5、，需同时变更积分时间常数的大小。3.3方案三8038集成函数发生器是一种多用途的波形发生器，可以干脆用来产生正弦波、方波、三角波和锯齿波。图4利用ICL8038芯片构成8038集成函数发生器综上所述，我们选择方案二。4单元电路的设计4.1正弦波发生器RC振荡电路由RC串并联选频网络和反向相放大电路组成，图中RC选频网络形成负反馈电路。图5-1正弦波波发生电路在图5-1电路中,当R1=R2=R，C1=C2=C时则（5-1）当频率时，依据幅度平衡条件，只有电路才能维持振荡。令C=100Nf,R44)+20;/占空比限制在20(20%)83(83%)之间/采集到的数据是01023/右移四位就是063

6、/加20就是2083/总采样点数是100点/占空比就是20/100=20%83/100=83%之间（5）端口I/O与中断MSP430有P1、P2一共十六个通用IO口。其功能安排如下端口功能I/O方向P2.0P2.7输出8位数据到DAC输出P1.0按键中断，切换波形输入P1.1按键中断，增加频率输入P1.2按键中断，减小频率输入P1.3DAC的WR信号输出P1.4ADC10的模拟输入口输入主要初始化端口方向、功能以及中断，程序如下：voidinit_port_io(void)P2DIR=P2_OUT_PORTS;/设置输出端口P2.0P2.7P2REN=0x00;/不运用上/下拉电阻P2SEL=

7、0x00;/端口的功能为IOP2SEL2=0x00;/端口的功能为IOP1DIR/P1.0P1.1p1.2p1.4输入P1DIR|=P1_OUT_PORTS;/P1.3输出给DACWRP1REN=0x00;P1SEL=0x00;P1SEL2=0x00;voidinit_port_interrupt(void)P1IES|=P1_INTERRUPT;/相应位置1表示下降沿触发P1IE|=P1_INTERRUPT;/输入位中断使能P1IFG/清除标记位五、功能实现1、波形输出及切换波形的输出主要靠定时器周期性触发中断，然后将波形值数组中的值依次循环写到P2上。流程图如下：波形切换靠按键中断以及变更

8、波形类型标记变量curr_signal_type实现，流程图如下：获得如下结果：2、频率调整波形的频率调整通过变更计时器初值TACCR0来实现，所需的频率计算公式为波频率=CPU时钟频率/(采样点数*定时器初值)流程图如下：为了能够使得频率可达到2000Hz，须要适当减小采样点数。在没有实现最大2000Hz时，采样电视为200点，将点数削减到100点，并适当减小DAC的WR信号的宽度，以达到在更高速的状况下能够将数据写入DAC。结果如下。产生5Hz的正弦波：产生2.145KHz的正弦波3、占空比调整占空比的调整主要靠ADC10采集电位器输入电压并根据肯定的算法算出高电平持续的点数duty_ci

9、rcle来表示占空比。采集转换的流程图如下相应的产生方波的逻辑为：20%占空比：80%占空比：六、问题及解决方案1、三角波和方波没有波形最起先三角波的每一个采样点的值是由程序计算出来的，程序如下所示：case1:/triangleif(point_now#defineSWITCH_SIG_TYPE(BIT0)/P1.0#defineADD_FREQ(BIT1)/P1.1#defineSUB_FREQ(BIT2)/P1.2#defineDAC_WR(BIT3)/P1.3#defineADC10_IN_PORT(BIT4)/P1.4#defineP1_IN_PORTS(SWITCH_SIG_TYP

10、E+ADD_FREQ+SUB_FREQ+ADC10_IN_PORT)#defineP1_OUT_PORTSDAC_WR/3:DACWR#defineP1_INTERRUPT(SWITCH_SIG_TYPE+ADD_FREQ+SUB_FREQ)#defineP2_OUT_PORTS(0xff)/DACdatain#defineTOTAL_SAMPLING_POINTS100#defineMAX_FREQ_STEPS400#defineENABLE_WR_PORTP1OUTinttccr0_now;uintccr0_idx;ucharpoint_now;intpush_key;intduty_ci

11、rcle;constlongtccr0_tableMAX_FREQ_STEPS=32000,16000,10666,8000,6400,5333,4571,4000,3555,3200,2909,2666,2461,2285,2133,2000,1882,1777,1684,1600,1523,1454,1391,1333,1280,1230,1185,1142,1103,1066,1032,1000,969,941,914,888,864,842,820,800,780,761,744,727,711,695,680,666,653,640,627,615,603,592,581,571,5

12、61,551,542,533,524,516,507,500,492,484,477,470,463,457,450,444,438,432,426,421,415,410,405,400,395,390,385,380,376,372,367,363,359,355,351,347,344,340,336,333,329,326,323,320,316,313,310,307,304,301,299,296,293,290,288,285,283,280,278,275,273,271,268,266,264,262,260,258,256,253,251,250,248,246,244,2

13、42,240,238,237,235,233,231,230,228,226,225,223,222,220,219,217,216,214,213,211,210,209,207,206,205,203,202,201,200,198,197,196,195,193,192,191,190,189,188,187,186,184,183,182,181,180,179,178,177,176,175,174,173,172,172,171,170,169,168,167,166,165,164,164,163,162,161,160,160,159,158,157,156,156,155,1

14、54,153,153,152,151,150,150,149,148,148,147,146,146,145,144,144,143,142,142,141,140,140,139,139,138,137,137,136,136,135,135,134,133,133,132,132,131,131,130,130,129,129,128,128,127,126,126,125,125,125,124,124,123,123,122,122,121,121,120,120,119,119,118,118,118,117,117,116,116,115,115,115,114,114,113,1

15、13,113,112,112,111,111,111,110,110,109,109,109,108,108,108,107,107,107,106,106,105,105,105,104,104,104,103,103,103,102,102,102,101,101,101,100,100,100,100,99,99,99,98,98,98,97,97,97,96,96,96,96,95,95,95,94,94,94,94,93,93,93,93,92,92,92,91,91,91,91,90,90,90,90,89,89,89,89,88,88,88,88,87,87,87,87,86,8

16、6,86,86,86,85,85,85,85,84,84,84,84,83,83,83,83,83,82,82,82,82,82,81,81,81,81,81,80,80,80,78,75;/cpu_freq/ccr0=-/sig_freqtotal_sampling_pointsconstucharsin_dataTOTAL_SAMPLING_POINTS=127,135,143,151,159,167,174,182,189,196,203,209,215,221,226,231,235,239,243,246,249,251,253,254,254,254,254,253,252,250

17、,247,245,241,237,233,228,223,218,212,206,199,192,185,178,171,163,155,147,139,131,123,115,107,99,91,83,76,69,62,55,48,42,36,31,26,21,17,13,9,7,4,2,1,0,0,0,0,1,3,5,8,11,15,19,23,28,33,39,45,51,58,65,72,80,87,95,103,111,119,127;constuchartria_dataTOTAL_SAMPLING_POINTS=0,5,10,15,20,26,31,36,41,46,52,57,

18、62,67,72,78,83,88,93,98,104,109,114,119,124,130,135,140,145,150,156,161,166,171,176,182,187,192,197,202,208,213,218,223,228,234,239,244,249,255,255,249,244,239,234,228,223,218,213,208,202,197,192,187,182,176,171,166,161,156,150,145,140,135,130,124,119,114,109,104,98,93,88,83,78,72,67,62,57,52,46,41,

19、36,31,26,20,15,10,5,0;#pragmavector=TIMER0_A0_VECTOR_interruptvoidtimer_A0(void)if(point_now=TOTAL_SAMPLING_POINTS)point_now=0;switch(curr_signal_type)case0:/sin;write_dac(sin_datapoint_now);break;case1:/trianglewrite_dac(tria_datapoint_now);break;case2:/boxif(point_now=3)curr_signal_type=0;elseif(p

20、ush_keyif(ccr0_idx=MAX_FREQ_STEPS)ccr0_idx=0;tccr0_now=tccr0_tableccr0_idx;elseif(push_keyif(ccr0_idx=MAX_FREQ_STEPS)ccr0_idx=MAX_FREQ_STEPS-1;tccr0_now=tccr0_tableccr0_idx;P1IFG/清除标记位voidinit_vars()curr_signal_type=0;point_now=0;ccr0_idx=MAX_FREQ_STEPS/2-1;/初始1kHztccr0_now=tccr0_tableccr0_idx;duty_

21、circle=TOTAL_SAMPLING_POINTS/2;/初始50%占空比voidinit_DCO()BCSCTL1=CALBC1_16MHZ;DCOCTL=CALDCO_16MHZ;BCSCTL2=SELM_1+DIVM_0;/selectDCOasthesourceofMCLKBCSCTL2/selectDCOasthesourceofSMCLKvoidinit_timer_A0(void)TACTL|=TASSEL_2+MC_2;/SMCLKsourceandModecontinousTACCR0=tccr0_now;TACCTL0|=CCIE;/interruptenable_E

22、INT();voidinit_port_io(void)P2DIR=P2_OUT_PORTS;/P211111111balloutP2REN=0x00;/disablepullup/downresistorP2SEL=0x00;/iofunctionisselectedP2SEL2=0x00;P1DIR/P1.0P1.1p1.2p1.4inP1DIR|=P1_OUT_PORTS;/P1.3forDACWRP1REN=0x00;P1SEL=0x00;P1SEL2=0x00;voidinit_port_interrupt(void)P1IES|=P1_INTERRUPT;/置1，下降沿触发P1IE

23、|=P1_INTERRUPT;/中断使能P1IFG/清除标记位voidinit_ADC10(void)ADC10CTL1|=INCH_4;/A4channelforconvertion,P1.4inADC10CTL1|=SHS_0;/Sample-and-holdsourceselectADC10SCADC10CTL1|=ADC10SSEL_3;/SMCLK16MADC10CTL1/straghtbinaryformatADC10CTL1|=CONSEQ_0;/SinglechannelsingleconvertionADC10AE0=ADC10_IN_PORT;/P1.4inADC10CTL

24、0/disableinterruptADC10CTL0|=SREF_1+ADC10SHT_0+REF2_5V+REFON;/V+=2.5V,V-=Vss=0ADC10CTL0/diasablerefouttop1.3p1.4ADC10CTL0|=ADC10ON;/enableadcvoidmain(void)WDTCTL=WDTPW|WDTHOLD;/Stopwatchdogtimerinit_vars();init_port_io();init_port_interrupt();init_DCO();init_timer_A0();init_ADC10();_bis_SR_register(

25、GIE);/全局中断使能while(1)ADC10CTL0/关闭采样使能while(ADC10CTL1/检测是否忙ADC10CTL0|=ENC+ADC10SC;/打开采样使能，起先转换while(ADC10CTL1/检测是否忙intadc_data=ADC10MEM;/读取数据duty_circle=(adc_data4)+20;/占空比限制在20(20%)83(83%)之间/采集到的数据是01023/右移四位就是063/加20就是2083/总点数是100点/占空比就是20/100=20%83/100=83%之间28/29篇3：外文翻译-基于DDS参数可调谐波信号发生器的探讨外文翻译-基于DD

26、S参数可调谐波信号发生器的探讨 本文关键词：可调，外文，谐波，翻译，参数外文翻译-基于DDS参数可调谐波信号发生器的探讨 本文简介：附录AResearchofParameterAdjustableHarmonicSignalGeneratorBasedonDDSLIWeiCollegeofComputerandInformationEngineeringHohaiUniversityChangzhou,213022,China外文翻译-基于DDS参数可调谐波信号发生器的探讨 本文内容：附录AResearchofParameterAdjustableHarmonicSignalGenerator

27、BasedonDDSLIWeiCollegeofComputerandInformationEngineeringHohaiUniversityChangzhou,213022,Chinaemail protectedZHANGJinboCollegeofComputerandInformationEngineeringHohaiUniversityChangzhou,213022,Chinaemail protectedAbstractHarmonicsignalgeneratorwhosefrequency,phaseandharmonicproportionaread

28、justableisdesignedforthedetectingequipmentofpowersystem.TheprincipleofDDSandthedesignrequirementareintroduced.ThenthealgorithmofROMcompressionbasedonthesymmetryofsinewaveisexpounded.Finally,usingAlteraFPGA,thedetaildesignofthewholesystemispresentedandtestwaveformsaregiven.Testresultsindicatethatthes

29、ystemfulfilsthedesignrequirements.1.IntroductionAnidealpowersystemsuppliespowerwithsinewave,butthepracticalwaveformofpowersupplyoftenhasmanyharmoniccomponents.Thebasicreasonofharmonicisthatthepowersystemsuppliespowertotheelectricalequipmentwithnonlinearcharacteristic.Thesenonlinearloadsfeedhigherhar

30、monicbacktothepowersupply,andmakethewaveformofcurrentandvoltageinpowersystemproduceseriousdistortion.Inthedetectionfieldofpowersystem,standardsignalgeneratorswhichcansimulatethepowerharmonicarehighlyneededtocalibratethepowerdetectingequipment,suchasphasedetector,PDdetector,andsoon.Sotheresearchofpar

31、ameteradjustableharmonicsignalgeneratorprovidestheexactbasisforthestableoperationofpowerdetectingequipment,andhasgreateconomicbenefitandsocialvalue.2.PrincipleofdirectdigitalsynthesisDirectdigitalsynthesis(DDS)isanewfrequencysynthesistechnologywhichdirectlysynthesizeswaveformonthebasisofphase.Usingt

32、herelationshipbetweenphaseandamplitude,thephaseofwaveformissegmentedandassignedrelevantaddresses.Ineachclockperiod,theseaddressesareextractedandtherelevantamplitudesaresampled.Theenvelopeofthesesampledamplitudesistheexpectedwaveform.Iftheclockfrequencyisconstant,thefrequencyofoutputsignalisadjustabl

33、ewithdifferentextractedstepsofaddresses.DDSiscomposedofphaseaccumulator,ROMtable,DACandLPF.Ineachclockperiod,theoutputofphaseaccumulatorisaccumulatedwithfrequencycontrolword,andhighL-bitoftheoutputareusedasaddresstoquerytheROMtable.IntheROM,theseaddressesareconvertedtothesampledamplitudesoftheexpect

34、edwaveform.ThenDACconvertsthesampledamplitudestoladderwave.IntheLPF,theladderwaveissmoothed,andtheoutputisthecontinuousanalogwaveform.Supposethattheclockfrequencyisfc,frequencycontrolwordisK,phaseaccumulatorisN-bit,thenoutputfrequencyisfout=(K/2N)fc,frequencyresolutionisfmin=fc/2N.AccordingtotheNyqu

35、istSampleCriterion,outputfrequencyupperlimitisfmax0.5fc.Becauseofthenon-idealcharacteristicofLPF,outputfrequencyupperlimitofDDSisfmax=0.4fc.3.Schemedesign3.1.DesignrequirementsThegoalofthesystemistodesignaharmonicsignalgenerator,whosefrequency,phaseandharmonicproportionareadjustable.Theoutputwavefor

36、miscomposedoffundamentalwave,3thharmonic,5thharmonicand7thharmonic.Frequencyresolutionis1Hz.Theadjustablerangeofinitialphaseis02anditsresolutionis1o.Theadjustablerangeofharmonicproportionis050%anditsresolutionis1%.Accordingtothedesignrequirements,systemclockfrequencyis15MHzandphaseaccumulatoris24-bi

37、t.InordertomakethemostofEAB,2118bitsROMtableisadopted.11-bitphasecontrolwordisusedtomeettherequirementofinitialphaseresolution.7-bitproportioncontrolwordisadoptedtorealizethesettingofharmonicproportion.3.2.AlgorithmofROMcompressionAsisknown,phasetruncationerroristhemainfactorofoutputwaveformdistorti

38、on.Toavoidthis,theROMsizemustbeexponentiallyincreased,howevertheEABofFPGAislimited.SothealgorithmofROMcompressionbasedonthesymmetryofsinewaveisadoptedinthesystem.Sinewaveofoneperiodisdividedinto4sections:0/2、/2、3/2、3/22.Usingthesymmetryofsinewave,sampledamplitudesofthefirstsectionarestoredintheROMta

39、ble.Byaddressconversionandamplitudeconversion,sampledamplitudesofoneperiodsinewavecanbegenerated.Bythismeans,theROMsizeisaquarteroftheprevioussize.InthesameROM,samplingpointscanbeincreasedby4timeswiththismethod.SampledamplitudesofquarterwavearestoredintheROMtable.Theoutputaddressofphaseaccumulatoris

40、(L+2)-bit.ThelowL-bitareusedtoquerytheROMtablewhilethehigh2-bitareusedtoidentifyphasesections.Whenthehighestbitis1,theoutputofROMtableshouldbesymmetricallyconvertedbytheamplitudeconvertor.Whenthesecondhighestbitis1,theL-bitaddressshouldbesymmetricallyconvertedbytheaddressconvertor.4.SystemdesignbasedonFPGAThesystemcanbedividedintotwofunctionmodules:sinewavegenerationmoduleandharmonicsynthesismodule.