电子科大罗萍模拟集成电路期末试题(共4页).doc

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1、精选优质文档-倾情为你奉上电子科技大学二零零 四 至二零零 五 学年第 二 学期期 中 微电子电路设计课程考试题（ 120 分钟） 考试形式： 闭卷 考试日期 2005年 5 月 日一二三四五六七八九十总分评卷教师1. Identify the source, drain, gate and bulk terminals, and find the current I in the transistors in the following Figure. Assume ，VTN=0.75V. (16pts) (problem4.3)Solution: (a) (b) 2. Design the

2、 bias circuit in the following figure to give the Q-point of and if the transistor current gain is and .What is the Q-point if the current gain of the transistor is actually 40? (15 pts) ( problem 5.62 ) Solution: 3. Find VOH, VOL and the power dissipation (for vo=VOL) for the logic inverter with th

3、e saturated load in the following figure. Assume, and ，. (16 pts) (Problem7.12m) Solution: , Checking: 4. Design a CMOS logic gate that implements the logic function based on the CMOS inverter. Select the transistor sizes with the same delay as that of the reference inverter whose ,. ( 20 pts).Solut

4、ion: 5. Find the poles and zeros of the following transfer function, and draw its asymptote Bode plot of the magnitude. (17pts)Solution：Zeros: sz1=0, s z2=-50Poles: s=-10, s=-200, s=-1000, s=-1000, s=-10000 6. Draw the output voltage waveform for the circuit in the following figure for the triangular input waveform shown. (16pts) Solution:专心-专注-专业