2022年毕业设计方案英文文献单片机中英文文献翻译.docx

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1、AT89C51的简况The General Situation of AT89C51Chapter 1 The application of AT89C51Microcontrollersareusedinamultitudeofcommercial applicationssuchasmodems, motor-controlsystems,airconditioner controlsystems,automotiveengineandamongothers.Thehigh processingspeedandenhancedperipheralsetofthese microcontro

2、llersmake them suitableforsuchhigh-speed event-based applications. However, these critical application domains alsorequirethatthesemicrocontrollersarehighlyreliable.Thehighreliability and low market risks can be ensured by a robust testingprocessand a propertoolsenvironmentforthevalidationofthese mi

3、crocontrollers both at the component and at the system level. IntelPlaformEngineeringdepartmentdevelopedanobject-orientedmulti- threadedtestenvironmentforthevalidationofitsAT89C51 automotivemicrocontrollers.Thegoalsofthisenvironmentwas not onlytoprovidearobusttestingenvironmentfortheAT89C51 automoti

4、ve microcontrollers, but to develop an environment which canbeeasilyextendedand reusedforthevalidationofseveralother future microcontrollers. The environment was developed in conjunctionwith Microsoft Foundation Classes AT89C51. The paper describes thedesign and mechanism of this test environment, i

5、ts interactions withvarioushardware/softwareenvironmentalcomponents,and how touse AT89C51.1.1 IntroductionThe 8-bitAT89C51 CHMOSmicrocontrollersaredesignedtohandle high-speedcalculationsandfastinput/outputoperations.MCS 51 microcontrollersaretypicallyusedforhigh-speedeventcontrol systems. Commercial

6、 applications include modems,motor-control systems,printers,photocopiers,airconditionercontrolsystems,disk drives,andmedicalinstruments.The automotiveindustryuseMCS 51 microcontrollersinengine-controlsystems,airbags,suspension19 / 18systems, and antilock braking systems ABS. The AT89C51 is especiall

7、y well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, suchasautomotivepower-traincontrol,vehicledynamicsuspension, antilockbraking,andstabilitycontrolapplications.Becauseof thesecriticalapplications,themarketrequiresareliablecost- effecti

8、vecontrollerwitha lowinterruptlatencyresponse,ability toservicethehighnumber of time and event driven integratedperipheralsneeded inrealtimeapplications,and a CPU withabove average processing power in a single package. The financial and legalrisk of having devices that operate unpredictably is very

9、high. Onceinthemarket,particularlyinmissioncriticalapplicationssuchas anautopilotoranti-lockbrakingsystem,mistakesare financiallyprohibitive.Redesigncostscan runashighasa$500K, much more ifthefixmeans 2backannotatingitacrossaproduct family that share the same core and/or peripheral design flaw. In a

10、ddition, field replacements of components is extremely expensive, asthedevicesaretypicallysealedinmoduleswithatotalvalueseveral times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carriedoutatboththecomponent levelandsystemlevelun

11、derworstcase environmentalandvoltageconditions.Thiscompleteandthorough validationnecessitatesnotonlyawell-definedprocessbutalsoa properenvironmentand toolstofacilitateand executethemission successfully.Intel Chandler Platform Engineering group provides postsiliconsystemvalidationSVofvariousmicro-con

12、trollersand processors.The systemvalidationprocesscanbe brokenintothree major parts.The type of the device and its application requirementsdetermine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4KbytesofFlash,128bytesofRAM, 32I/Olines,tw

13、o16- bittimer/counters,afivevectortwo-levelinterruptarchitecture,a full duple ser-ial port, on-chip oscillator and clock circuitry.Inaddition,theAT89C51 isdesignedwithstaticlogicforoperationdown tozerofrequencyand supportstwosoftwareselectablepower savingmodes. The IdleMode stopstheCPU whileallowing

14、theRAM, timer/counters,serialportandinterruptsys-temtocontinue functioning. The Power-down Mode saves the RAM contents but freezesthe oscil lator disabling all other chip functions until the nexthardware reset.Figure 1-2-1Block Diagram1-3Pin Description VCC Supply voltage. GND Ground.Port 0 ：Port 0

15、is an 8-bit open-drain bi-directional I/O port. Asan output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworderaddress/data busduring accesses to external program and da

16、ta memory.In this mode P0 has internalpullups.Port0 also receives the codebytes during Flash programming,and outputs the codebytes during program verification.External pullups are required during programverification.Port 1 ： Port 1 is an 8-bit bi-directional I/O port with internalpullups.ThePort1out

17、putbufferscansink/so-urcefourTTL inputs.When 1s are written to Port 1 pins they are pulled high by theinternalpullupsand can be usedas inputs.As inputs,Port1 pins thatareexternallybeingpulledlowwillsourcecurrentIIL becauseoftheinternalpullups.Port1 alsoreceivesthelow-order address bytes during Flash

18、 programming and verification.Port 2 ： Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternal pullups and can beused as inputs. Asinputs, Port 2 pins that are externally being

19、 pulled low will source current IIL because of theinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemory and duringaccessestoPort2 pins that are externally being pulled low will source current IILbecause of the internal pullups.Port 2 emits the high-order addressbyt

20、e during fetches from external program memory and during accessestoexternaldatamemory thatuse16-bitaddressesMOVXDPTRIn. this application, it uses strong internal pull-ups when emitting 1s.Duringaccessestoexternaldatamemory thatuse8-bitaddresses MOVX RI,Port2emitsthecontentsoftheP2 SpecialFunction Re

21、gister.Port2 alsoreceivesthehigh-orderaddressbitsandsome control signals durin Flash programming and verification.Port 3 ： Port 3 is an 8-bit bi-directional I/O port with internalpullups.ThePort3outputbufferscansink/sou-rcefourTTL inputs.When 1s are written to Port 3 pins they are pulled high by the

22、internalpullupsandcanbeused asinputs.As inputs,Port3pins thatareexternallybeingpulledlowwillsourcecurrentIIL because of the pullups.Port3alsoservesthefunctionsofvariousspecialfeaturesofthe AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles whilethe oscillator is runni

23、ng resets the device.ALE/PRO：G Address Latch Enable output pulse for latching the lowbyte of the address duringaccesses to external memory.This pin is also the program pulse input PROG during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and

24、may be used for external timing or clockingpurposes. Note, however, that one ALEpulse is skipped duri-ng each accesstoexternalDataMemory.Ifdesired,ALEoperationcanbe disabled by setting bit 0 of SFR location 8EH. With the bit set, ALEis active onlyduring a MOVX or MOVC instruction. Otherwise, the pin

25、isweaklypulledhigh.SettingtheALE-disablebithas no effectif the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external programmemory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that

26、two PSEN activations are skipped during each access toexternal data memory.EA/VPP： External Access Enable. EA must be strapped to GND inorder to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lockbit 1 is programmed, EA will

27、 be internally latched onreset.EA shouldbestrappedtoVCC forinternalprogramexecutions.Thispin alsreceives the 12-volt programming enable voltage VPP during Flash programming, forparts that require 12-volt VPP.XTAL1： Input to the inverting oscillator amplifier and input tothe internal clock operatingc

28、ircuit.XTAL2 ： Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifierwhich can be configured for use as an on- chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be

29、used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 isdriven as shown inFigure 2.There are no requirements on the dutycycle of the external clock signal, sincethe input to the internal clocking circuitry is through a divide-by-two flip-flop, butminimu

30、mandmaximum voltagehighandlowtimespecificationsmustbe observed.IdleModeIn idlemode, theCPU putsitselftosleepwhile alltheonchipperipheralsremainactive.Themode isinvokedby software. The content of the on-chip RAM and all thespecial functionsregistersremainunchangedduringthismode.Theidlemode can beterm

31、inatedbyanyenabledinterruptorbyahardwarereset.It should be noted that whenidle is terminated by a hard ware reset, thedevice normally resumes program execution,from where it left off, uptotwomachinecyclesbeforetheinternalresetalgorithm takescontrol.On-chiphardwareinhibitsaccesstointernalRAM in this

32、event, but access to theport pins is not inhibited. To eliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleis terminated by reset, the instruction following the one that invokesIdleshould not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the os

33、cillator is stopped, and the instruction that invokes power-down is the last instruction executed.The on-chip RAMand Special Function Registers retain their values until the power-down mode is terminated. The only exit from power- down is a hardware reset. Reset redefines the SFRs but does not chang

34、e the on-chip RAM. The reset should not be activated before VCCisrestoredtoitsnormaloperatingleveland mustbeheldactive longenoughtoallowtheoscillatortorestartandstabilize.The AT89C51 codememory arrayisprogrammedbyte-bybyteineither programming mode. To program any nonblank byte in the on-chip FlashMe

35、mory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBeforeprogrammingtheAT89C51, theaddress,dataandcontrol signalsshouldbesetupaccordingtotheFlashprogrammingmode tableand Figure3and Figure4.To programtheAT89C51, takethe following steps.1.Input the desired memory l

36、ocation on the addresslines.2.Inputtheappropriatedatabyteonthedatalines.3.Activate the correct combination of control signals. 4. Raise EA/VPPto 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-writecycle is self-timed

37、and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire arrayoruntiltheend oftheobjectfileisreached.DataPolling:The AT89C51 features Data Polling to indicate the end of a write cycle.During a write cycle, an attempted read of the last byte writ

38、ten will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a writecycle has been initiated.2.1Ready/Busy:The progressofbyteprogrammingcanalsobemonitor

39、edbythe RDY/BSY output signal. P3.4 is pulled low after ALE goes high duringprogrammingtoindicateBUSY.P3.4ispulledhighagainwhenprogramming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmedcodedatacanbereadbackviatheaddressanddatalinesfor verif

40、ication. The lock bits cannot be verified directly. Verificationofthelockbitsisachievedbyobservingthattheirfeaturesareenabled.Figure 2-1-1 Programming the FlashFigure 2-2-2 Verifying the Flash2.2 Chip Erase:The entire Flash array is erased electrically by using the propercombination of control signa

41、ls and by holding ALE/PROG low for 10 ms.The code array is written with all“ 1 ” s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:Thesignaturebytesarereadbythesame procedureasa normal verification of locations 030H, 031H, and 03

42、2H, except that P3.6 andP3.7mustbepulledtoalogiclow.Thevaluesreturnedareasfollows.030H = 1EH indicates manufactured by Atmel031H = 51H indicates 89C51 032H = FFH indicates 12V programming 032H = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written an

43、d the entire array can be erased by using the appropriate combination of controlsignals. The writeoperation cycle isselftimed and onceinitiated,will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information ha

44、ndled by an electronic system existsas a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into anumber of operations which modify the data in some way, so that theprocess of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converterADCis used to convert a continuously variab