verilog设计一个串行数据检测器(共3页).doc

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1、精选优质文档-倾情为你奉上题目：设计一个串行数据检测器。要求是：连续4个或4个以上为1时输出为1，其他输入情况下为0。代码如下：module four_one( x, z, clk, rst, state);input x, clk, rst;output z;output2:0 state;reg2:0 state;wire z;parameter IDLE = d0, A = d1, B = d2,C = d3,D = d4;assign z = (state = D) ? 1 : 0;always (posedge clk or negedge rst)if (!rst)begin st

2、ate = IDLE;endelsecasex (state)IDLE: if (x = 1)begin state = A;endelsebeginstate = IDLE;endA: if (x = 1)begin state = B;endelsebeginstate = IDLE;endB: if (x = 1)begin state = C;endelsebeginstate = IDLE;endC: if (x = 1)begin state = D;endelsebeginstate = IDLE;endD: if (x =1)begin state = D;endelsebeg

3、instate = IDLE;enddefault: state = IDLE;endcaseendmodule测试代码如下：timescale 1ns / 1psmodule four_one_tst;reg x;reg clk, rst;wire z;wire 2:0 state;always #20 clk = clk;always (posedge clk)begin#20 x = $random%2;endfour_one uut (.x(x), .z(z), .clk(clk), .rst(rst), .state(state);initialbeginx = 0;clk = 0;rst = 1;#2 rst = 0;#50 rst = 1; #500 $stop;end endmodule使用ModelSim仿真波形：专心-专注-专业