QRC_ARMSIDE.PDF

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1、ARMInstruction SetQuick Reference CardKey to TablescondRefer to Table Condition Field cond. Omit for unconditional execution.Refer to Table Addressing Mode 2.Refer to Table Flexible Operand 2. Shift and rotate are only available as part of Operand2.Refer to Table Addressing Mode 2 (Post-indexed only

2、).Refer to Table PSR fields.Refer to Table Addressing Mode 3.Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register)Refer to Table Addressing Mode 4 (Block load or Stack pop).SUpdates condition flags if S present.Refer to Table Addressing Mode 4 (Block store or Stac

3、k push).C*, V*Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later.Refer to Table Addressing Mode 5.QSticky flag. Always updates on overflow (no S option). Read and reset using MRS and MSR.A comma-separated list of registers, enclosed in braces, and .x,yB mean

4、ing half-register 15:0, or T meaning 31:16.!Updates base register after data transfer if ! present.A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.+/-+ or . (+ may be omitted.)A 10-bit constant, formed by left-shifting an 8-bit value by two bits.Refer to Table AR

5、M architecture versions.OperationAssemblerS updatesQ ActionMoveMoveMOVcondS Rd, N ZCRd := Operand2NOTMVNcondS Rd, N ZCRd := 0 xFFFFFFFF EOR Operand2PSR to register3MRScond Rd, Rd := PSRregister to PSR3MSRcond _, RmPSR := Rm (selected bytes only)immediate to PSR3MSRcond _, #PSR := immed_8r (selected

6、bytes only)40-bit accumulator to registerXS MRAcond RdLo, RdHi, AcRdLo := Ac31:0, RdHi := Ac39:32register to 40-bit accumulatorXS MARcond Ac, RdLo, RdHiAc31:0 := RdLo, Ac39:32 := RdHiArithmeticAddADDcondS Rd, Rn, N ZCVRd := Rn + Operand2with carryADCcondS Rd, Rn, N ZCVRd := Rn + Operand2 + Carrysatu

7、rating5EQADDcond Rd, Rm, RnQ Rd := SAT(Rm + Rn)double saturating5EQDADDcond Rd, Rm, RnQ Rd := SAT(Rm + SAT(Rn * 2)SubtractSUBcondS Rd, Rn, N ZCVRd := Rn Operand2with carrySBCcondS Rd, Rn, N ZCVRd := Rn Operand2 NOT(Carry)reverse subtractRSBcondS Rd, Rn, N ZCVRd := Operand2 Rnreverse subtract with ca

8、rryRSCcondS Rd, Rn, N ZCVRd := Operand2 Rn NOT(Carry)saturating5EQSUBcond Rd, Rm, RnQ Rd := SAT(Rm Rn)double saturating5EQDSUBcond Rd, Rm, RnQ Rd := SAT(Rm SAT(Rn * 2)Multiply2MULcondS Rd, Rm, RsN Z C*Rd := (Rm * Rs)31:0accumulate2MLAcondS Rd, Rm, Rs, RnN Z C*Rd := (Rm * Rs) + Rn)31:0unsigned longMU

9、MULLcondS RdLo, RdHi, Rm, RsN Z C* V*RdHi,RdLo := unsigned(Rm * Rs)unsigned accumulate longMUMLALcondS RdLo, RdHi, Rm, RsN Z C* V*RdHi,RdLo := unsigned(RdHi,RdLo + Rm * Rs)signed longMSMULLcondS RdLo, RdHi, Rm, RsN Z C* V*RdHi,RdLo := signed(Rm * Rs)signed accumulate longMSMLALcondS RdLo, RdHi, Rm,

10、RsN Z C* V*RdHi,RdLo := signed(RdHi,RdLo + Rm * Rs)signed 16 * 16 bit5ESMULxycond Rd, Rm, RsRd := Rmx * Rsysigned 32 * 16 bit5ESMULWycond Rd, Rm, RsRd := (Rm * Rsy)47:16signed accumulate 16 * 16 bit5ESMLAxycond Rd, Rm, Rs, RnQ Rd := Rn + Rmx * Rsysigned accumulate 32 * 16 bit5ESMLAWycond Rd, Rm, Rs,

11、 RnQ Rd := Rn + (Rm * Rsy)47:16signed accumulate long 16 * 16 bit5ESMLALxycond RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rmx * RsyMultiply with internal 40-bit accumulateXS MIAcond Ac, Rm, RsAc := Ac + Rm * Rspacked halfwordXS MIAPHcond Ac, Rm, RsAc := Ac + Rm15:0 * Rs15:0 + Rm31:16 * Rs31:16halfwo

12、rdXS MIAxycond Ac, Rm, RsAc := Ac + Rmx * RsyCount leading zeroes5CLZcond Rd, RmRd := number of leading zeroes in RmLogicalTestTSTcond Rn, N ZCUpdate CPSR flags on Rn AND Operand2Test equivalenceTEQcond Rn, N ZCUpdate CPSR flags on Rn EOR Operand2ANDANDcondS Rd, Rn, N ZCRd := Rn AND Operand2EOREORco

13、ndS Rd, Rn, N ZCRd := Rn EOR Operand2ORRORRcondS Rd, Rn, N ZCRd := Rn OR Operand2Bit ClearBICcondS Rd, Rn, N ZCRd := Rn AND NOT Operand2CompareCompareCMPcond Rn, N ZCVUpdate CPSR flags on Rn Operand2negativeCMNcond Rn, N ZCVUpdate CPSR flags on Rn + Operand2No OpNo operationNOPNoneARM Instruction Se

14、tQuick Reference CardOperationAssemblerActionNotesBranchBranchBcond labelR15 := labellabel must be within 32Mb ofcurrent instruction.with linkBLcond labelR14 := R15 4, R15 := labellabel must be within 32Mb ofcurrent instruction.and exchange4T,5 BXcond RmR15 := Rm, Change to Thumb if Rm0 is 1with lin

15、k and exchange (1)5TBLX labelR14 := R15 4, R15 := label, Change to Thumb Cannot be conditional.label must be within 32Mb ofcurrent instruction.with link and exchange (2)5BLXcond RmR14 := R15 4, R15 := Rm31:1Change to Thumb if Rm0 is 1LoadWordLDRcond Rd, Rd := addressRd must not be R15.User mode priv

16、ilegeLDRcondT Rd, Rd must not be R15.branch ( 5T: and exchange)LDRcond R15, R15 := address31:1( 5T: Change to Thumb if address0 is 1)ByteLDRcondB Rd, Rd := ZeroExtendbyte from addressRd must not be R15.User mode privilegeLDRcondBT Rd, Rd must not be R15.signed4LDRcondSB Rd, Rd := SignExtendbyte from

17、 addressRd must not be R15.Halfword4LDRcondH Rd, Rd := ZeroExtenthalfword from addressRd must not be R15.signed4LDRcondSH Rd, Rd := SignExtendhalfword from addressRd must not be R15.Doubleword5E* LDRcondD Rd, Rd := address, R(d+1) := address + 4Rd must be even, and not R14.Load multiplePop, or Block

18、 data loadLDMcond Rn!, Load list of registers from Rnreturn (and exchange)LDMcond Rn!, Load registers, R15 := address31:1( 5T: Change to Thumb if address0 is 1)and restore CPSRLDMcond Rn!, Load registers, branch ( 5T: and exchange),CPSR := SPSRUse from exception modes only.User mode registersLDMcond

19、 Rn, Load list of User mode registers from RnUse from privileged modes only.Soft preloadMemory system hint5E* PLD Memory may prepare to load from addressCannot be conditional.StoreWordSTRcond Rd, address := RdUser mode privilegeSTRcondT Rd, address := RdByteSTRcondB Rd, address7:0 := Rd7:0User mode

20、privilegeSTRcondBT Rd, address7:0 := Rd7:0Halfword4STRcondH Rd, address15:0 := Rd15:0Doubleword5E* STRcondD Rd, address := Rd, address + 4 := R(d+1)Rd must be even, and not R14.Store multiplePush, or Block data storeSTMcond Rn!, Store list of registers to RnUser mode registersSTMcond Rn!, Store list

21、 of User mode registers to RnUse from privileged modes only.SwapWord3SWPcond Rd, Rm, Rntemp := Rn, Rn := Rm, Rd := tempByte3SWPcondB Rd, Rm, Rntemp := ZeroExtend(Rn7:0),Rn7:0 := Rm7:0, Rd := tempCoprocessorsData operations2CDPcond , , CRd, CRn, CRm, Coprocessor definedAlternative operations5CDP2 , ,

22、 CRd, CRn, CRm, Cannot be conditional.Move to ARM reg from coproc2MRCcond , , Rd, CRn, CRm, Alternative moves5MRC2 , , Rd, CRn, CRm, Cannot be conditional.Two ARM register move5E* MRRCcond , , Rd, Rn, CRmMove to coproc from ARM reg2MCRcond , , Rd, CRn, CRm, Alternative moves5MCR2 , , Rd, CRn, CRm, C

23、annot be conditional.Two ARM register move5E* MCRRcond , , Rd, Rn, CRmLoad2LDCcond , CRd, Alternative loads5LDC2 , CRd, Cannot be conditional.Store2STCcond , CRd, Alternative stores5STC2 , CRd, Cannot be conditional.SoftwareinterruptSWIcond Software interrupt processor exception24-bit value encoded

24、in instruction.Breakpoint5BKPT Prefetch abort or enter debug stateCannot be conditional.ARM Addressing ModesQuick Reference CardAddressing Mode 2 - Word and Unsigned Byte Data TransferARM architecture versionsPre-indexedImmediate offsetRn, #+/-!nARM architecture version n and above.Zero offsetRnEqui

25、valent to Rn,#0nTT variants of ARM architecture version n and above.Register offsetRn, +/-Rm!MARM architecture version 3M, and 4 and above, except xM variants.Scaled register offset Rn, +/-Rm, LSL #!Allowed shifts 0-31nEAll E variants of ARM architecture version n and above.Rn, +/-Rm, LSR #!Allowed

26、shifts 1-32nE*E variants of ARM architecture version n and above, except xP variants.Rn, +/-Rm, ASR #!Allowed shifts 1-32XSXScale coprocessor instructionRn, +/-Rm, ROR #!Allowed shifts 1-31Rn, +/-Rm, RRX!Flexible Operand 2Post-indexedImmediate offsetRn, #+/-Immediate value#Register offsetRn, +/-RmLo

27、gical shift left immediateRm, LSL #Allowed shifts 0-31Scaled register offset Rn, +/-Rm, LSL #Allowed shifts 0-31Logical shift right immediateRm, LSR #Allowed shifts 1-32Rn, +/-Rm, LSR #Allowed shifts 1-32Arithmetic shift right immediateRm, ASR #Allowed shifts 1-32Rn, +/-Rm, ASR #Allowed shifts 1-32R

28、otate right immediateRm, ROR #Allowed shifts 1-31Rn, +/-Rm, ROR #Allowed shifts 1-31RegisterRmRn, +/-Rm, RRXRotate right extendedRm, RRXLogical shift left registerRm, LSL RsAddressing Mode 2 (Post-indexed only)Logical shift right registerRm, LSR RsPost-indexedImmediate offsetRn, #+/-Arithmetic shift

29、 right registerRm, ASR RsZero offsetRnEquivalent to Rn,#0Rotate right registerRm, ROR RsRegister offsetRn, +/-RmScaled register offset Rn, +/-Rm, LSL #Allowed shifts 0-31PSR fields(use at least one suffix)Rn, +/-Rm, LSR #Allowed shifts 1-32SuffixMeaningRn, +/-Rm, ASR #Allowed shifts 1-32cControl fie

30、ld mask bytePSR7:0Rn, +/-Rm, ROR #Allowed shifts 1-31fFlags field mask bytePSR31:24Rn, +/-Rm, RRXsStatus field mask bytePSR23:16xExtension field mask bytePSR15:8Addressing Mode 3 - Halfword, Signed Byte, and Doubleword Data TransferPre-indexedImmediate offsetRn, #+/-!Condition Field condZero offsetR

31、nEquivalent to Rn,#0MnemonicDescriptionDescription (VFP)RegisterRn, +/-Rm!EQEqualEqualPost-indexedImmediate offsetRn, #+/-NENot equalNot equal, or unorderedRegisterRn, +/-RmCS / HSCarry Set / Unsigned higher or sameGreater than or equal, or unorderedCC / LOCarry Clear / Unsigned lowerLess thanAddres

32、sing Mode 4 - Multiple Data TransferMINegativeLess thanBlock loadStack popPLPositive or zeroGreater than or equal, or unorderedIAIncrement AfterFDFull DescendingVSOverflowUnordered (at least one NaN operand)IBIncrement BeforeEDEmpty DescendingVCNo overflowNot unorderedDADecrement AfterFAFull Ascendi

33、ngHIUnsigned higherGreater than, or unorderedDBDecrement BeforeEAEmpty AscendingLSUnsigned lower or sameLess than or equalBlock storeStack pushGESigned greater than or equalGreater than or equalIAIncrement AfterEAEmpty AscendingLTSigned less thanLess than, or unorderedIBIncrement BeforeFAFull Ascend

34、ingGTSigned greater thanGreater thanDADecrement AfterEDEmpty DescendingLESigned less than or equalLess than or equal, or unorderedDBDecrement BeforeFDFull DescendingALAlways (normally omitted)Always (normally omitted)Addressing Mode 5 - Coprocessor Data TransferPre-indexedImmediate offsetRn, #+/-!Zero offsetRnEquivalent to Rn,#0Post-indexedImmediate offsetRn, #+/-UnindexedNo offsetRn, 8-bit copro. option