最新VHDL双语教学第3章(共91张PPT课件).pptx

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1、VHDLSynthesis & Simulation(Basic Language Items)第一页，共九十一页。AgendanEntitynArchitecturenLibrary & UsenPackagenConfiguration第二页，共九十一页。Basic Language Frameworklibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is port ( A, B, C : in std_logic; - Comments F : out std_logic );end XYZ;-architecture XYZ_ar

2、ch of XYZ isbegin F = (A and B) or (B and C) or (C and A); end XYZ_arch; 第三页，共九十一页。AgendanOverviewnPortnGenericnArchitecturenLibrary & UsenPackagenConfiguration第四页，共九十一页。Entitylibrary ieee;use ieee.std_logic_1164.all;- XYZ port ( A, B, C : in std_logic; F : out std_logic ); XYZ;-architecture XYZ_arc

3、h of XYZ isbegin F = (A and B) or (B and C) or (C and A);end XYZ_arch; 第五页，共九十一页。Entity Definition entity_name entity_name Generics; Ports; Other Declarative Parts; Statements; entity entity_nameentity_name ; 第六页，共九十一页。Entity Examples (ROM) ROM port ( D0 : out bit; D1 : out bit; D2 : out bit; D3 : o

4、ut bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) ); ROM;ROMA0A1A2A3A4A5A6A7D0D1D2D3D4D5D6D7第七页，共九十一页。Entity Examples (Adder) Full_Adder port (X, Y, Cin: in Bit; Cout, Sum: out Bit) ;Full_AdderXYCinSumCout第八页，共九十一页。Entity Examples (n-input AND) ANDN generic (wid : integer := 2); port

5、( X : in bit_vector(wid-1 downto 0); F : out bit ); X(0) X(1) X(2) X(wid-1) F 第九页，共九十一页。Entity Example (Empty Entity) Test_Bench Test_BenchTest_BenchSignal GeneratorTest Target第十页，共九十一页。AgendanOverviewnKeywordsnGenericnArchitecturenLibrary & UsenPackagenConfiguration第十一页，共九十一页。Entity Definition (Por

6、ts) entity_name entity_name Generics; Other Declarative Parts; Statements; entity entity_nameentity_name ; 第十二页，共九十一页。Port Example (ANDN)entity ANDN is generic (wid : integer := 2); ( X : in bit_vector(wid-1 downto 0); F : out bit );end; X(0) X(1) X(2) X(wid-1) F 第十三页，共九十一页。Port Examples (ROM)entity

7、 ROM is ( D0 : out bit; D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) );end ROM;ROMA0A1A2A3A4A5A6A7D0D1D2D3D4D5D6D7第十四页，共九十一页。Port Examples (Adder) Full_Adder (X, Y, Cin: in Bit; Cout, Sum: out Bit) ;end entity Full_Adder ;XYCinSumCout第十五页，共九十一页。P

8、ort Examples (n-input AND)entity ANDN is generic (wid : integer := 2); ( X : in bit_vector(wid-1 downto 0); F : out bit );end; X(0) X(1) X(2) X(wid-1) F 第十六页，共九十一页。Port Definition Port_Name, Port_Name : Dir Type:=Default_ValPort_Name, Port_Name : Dir Type:=Default_Val .Port_Name, Port_Name : Dir Typ

9、e:=Default_Val第十七页，共九十一页。Each Parts of Port A0, A1 : in std_logic; A2 : in std_logic := 1; F0 : buffer std_logic; F1 : out std_logic; F2 : inout std_logic Port Name Dir Type Default Value第十八页，共九十一页。Type of “Dir”nInnOutnInoutnBuffernLinkage第十九页，共九十一页。Signal Direction D Q D Q A0 (IN) A1 (IN) A2 (IN) F

10、0 (BUFFER) F1 (OUT) F2 (INOUT) Other ICOther IC第二十页，共九十一页。Dir Example D Q D Q A0 (IN) A1 (IN) A2 (IN) F0 (BUFFER) F1 (OUT) F2 (INOUT) A0, A1 : in std_logic A2 : in std_logic := 1 F0 : buffer std_logic F1 : out std_logic F2 : inout std_logic第二十一页，共九十一页。Use of Dirlibrary ieee;use ieee.std_logic_1164.a

11、ll;-entity ABC is port ( : std_logic; : std_logic; : std_logic; : std_logic );end ABC;-architecture ABC_arch of ABC isbegin process() begin if rising_edge() then = not ; = ; end if; end process; = when = 1 ELSE Z;end ABC_arch; 第二十二页，共九十一页。Type A0, A1 : in std_logic; A2 : in std_logic := 1; F0 : buff

12、er std_logic; F1 : out std_logic; F2 : inout std_logic Port Name Dir Type Default Value第二十三页，共九十一页。Typical Port TypenBitnBit_vectornStd_logicnStd_logic_vector第二十四页，共九十一页。Bitn1n0第二十五页，共九十一页。Bit_vectorport( X : in bit_vector(3 downto 0); F : out bit );X0X1X2X3FPort ( X0 : in bit; X1 : in bit; X2 : in

13、bit; X3 : in bit; F : out bit );Port ( X0, X1, X2, X3 : in bit; F : out bit );第二十六页，共九十一页。Std_logicnU, - UninitializednX, - Forcing Unknownn0, - Forcing 0n1, - Forcing 1nZ, - High Impedance nW, - Weak UnknownnL, - Weak 0 nH, - Weak 1 n- - Dont care第二十七页，共九十一页。Resolution Function Of Std_logicU X 01 Z

14、 W L H -U U U U U U U U U UX U X X X X X X X X0 U X 0 X 0000 X1 U X X 11111 XZ U X 01 Z W L H XW U X 01 W W W W XL U X 01 L W L W XH U X 01 H W W H X-U X X X X X X X X第二十八页，共九十一页。Std_logic_vectorport( X : in std_logic_vector(3 downto 0); F : out std_logic );X0X1X2X3F第二十九页，共九十一页。AgendanOverviewnKeywo

15、rdsnPortnArchitecturenLibrary & UsenPackagenConfiguration第三十页，共九十一页。Entity Definition (Generics) entity_name entity_name Ports; Other Declarative Parts; Statements; entity entity_nameentity_name ; 第三十一页，共九十一页。An AND Gate With Unknown Inputsentity ANDN is ( : integer := 2); port ( X : in bit_vector(-

16、1 downto 0); F : out bit );end ANDN; X(0) X(1) X(2) X(wid-1) F 第三十二页，共九十一页。Generic Definition ( Name , Name : DataType := DefaultValue Name , Name : DataType := DefaultValue Name , Name : DataType := DefaultValue);第三十三页，共九十一页。Generic Example (1)entity abcd is ( p_a : integer : = 2; p_b : integer : =

17、 7 ); port ( A : out bit_vector(0 to p_a - 1); F : in bit );end;第三十四页，共九十一页。Use of the Generic (ANDN.vhd)library ieee;use ieee.std_logic_1164.all;- is ( : integer := 2); port ( X : in bit_vector(-1 downto 0); F : out bit ); ;-architecture ANDN_arch of isbegin process(X) variable tmp : bit; begin tmp

18、 := 1; for i in -1 downto 0 loop tmp := tmp and X(i); end loop; F = tmp; end process;end ANDN_arch; X(0) X(1) X(2) X(wid-1) F 第三十五页，共九十一页。Use of the Generic (My_package.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;-package my_package is is

19、 generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); component; end my_package; 第三十六页，共九十一页。library ieee;use ieee.std_logic_1164.all;library work;use work.my_package.all;-entity SEE is port ( A : in bit_vector(3 downto 0); B : in bit_vector(1 downto 0); F1, F2 : ou

20、t bit );end SEE;-architecture SEE_arch of SEE isbegin U1: port map (A, F1); U2: port map (B, F2);end SEE_arch; Use of the Generic (see.vhd)U1A(0)A(1)A(2)A(3)F1U2B(1)B(3)F2第三十七页，共九十一页。AgendanOverviewnEntitynBlocknProcessnSubprogramnFunctionnProcedurenLibrary & UsenPackagenConfiguration第三十八页，共九十一页。Arc

21、hitecturelibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is port ( A, B, C : in std_logic; F : out std_logic );end XYZ;- XYZ_arch XYZ F = (A and B) or (B and C) or (C and A); XYZ_arch; 第三十九页，共九十一页。Architecture Definition arch_name entity_name architecture_declarative_part architecture_statement

22、_part architecture arch_name ;第四十页，共九十一页。Architecture Example (ABC.vhd)library ieee;use ieee.std_logic_1164.all;-entity ABC is port( A0,A1,A2 : in std_logic; F0 : buffer std_logic; F1 : out std_logic; F2 : inout std_logic );end ABC;- ABC_arch ABC process(A0) begin if rising_edge(A0) then F0 = not F0

23、; F1 = F2; end if; end process; F2 = A1 when A2 = 1 ELSE Z; ABC_arch; 第四十一页，共九十一页。Architecture Example (ANDN.vhd)library ieee;use ieee.std_logic_1164.all;-entity ANDN is generic (wid : integer := 2); port( X : in bit_vector(wid-1 downto 0); F : out bit );end ANDN;- ANDN process(X) variable tmp : bit

24、; begin tmp := 1; for i in wid-1 downto 0 loop tmp := tmp and X(i); end loop; F = tmp; end process; ; X(0) X(1) X(2) X(wid-1) F 第四十二页，共九十一页。Use of the Generic (see.vhd)library ieee;use ieee.std_logic_1164.all;library work;use work.my_package.all;-entity SEE is port ( A : in bit_vector(3 downto 0); B

25、 : in bit_vector(1 downto 0); F1, F2 : out bit );end SEE;- SEE_arch SEE U1: ANDN generic map(4) port map (A, F1); U2: ANDN port map (B, F2); SEE_arch; U1A(0)A(1)A(2)A(3)F1U2B(1)B(3)F2第四十三页，共九十一页。AgendanOverviewnEntitynKeywordsnProcessnSubprogramnFunctionnProcedurenLibrary & UsenPackage nConfiguratio

26、n第四十四页，共九十一页。Inside ArchitecturenHow to maintain large architecture?nHow to modulate the architecture code?nSeparate the architecture in to several partsnHow to separate the architecture?nVHDL language that can separate an architecturenBlock nProcess第四十五页，共九十一页。Example of Block (BLKBLK.vhd)library i

27、eee;use ieee.std_logic_1164.all;-entity blkblk is port(X: in std_logic; Y: out std_logic);end blkblk; blkblk_arch blkblk signal A, B: std_logic; signal C, D: std_logic; A = C; B = D; C = X; D = X; signal C, E: std_logic; C = A; E = B; signal E, F, G: std_logic; E = A; F = E; G = u2.E; Y = X and (A o

28、r B); blkblk_arch;第四十六页，共九十一页。Definition of BlockBlockLabel: ( GuardExpression) is Declarations; ConcurrentStatements; BlockLabel;第四十七页，共九十一页。Example of Block (BLKBLK.vhd)library ieee;use ieee.std_logic_1164.all;-entity blkblk is port(X: in std_logic; Y: out std_logic);end blkblk; blkblk_arch blkblk

29、 signal A, B: std_logic; signal C, D: std_logic; A = C; B = D; C = X; D = X; signal C, E: std_logic; C = A; E = B; signal E, F, G: std_logic; E = A; F = E; G = u2.E; Y = X and (A or B); blkblk_arch;第四十八页，共九十一页。Example of Block (Test_16.vhd) Blck_Test_1: (clock = 1 and ClockEVENT) Destination_1 = gua

30、rded Source;Destination_2 = Source; Blck_Test_1; Blck_Test_2: (Clock = 1 and not(ClockSTABLE) Destination_3 =guarded Source;Destination_4 =Source; Blck_Test_2;Monitor:variable Source_Var : NATURAL;variable Dest_1_Var, Dest_2_Var : NATURAL;variable Dest_3_Var, Dest_4_VAr : NATURAL Source_Var := Sourc

31、e;Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;wait on Destination_1,Destination_2, Destination_3,Destination_4; Monitor;Tick_Tock:wait for 10 ns;Clock =not clock; Tick_Tock; Source_Wave: Source =1 after 8 ns, 2 after 15 ns, 3 afte

32、r 16 ns, 4 after 17 ns, 5 after 18 ns,6 after 19 ns; Behave_1; Test_16 Test_16;Behave_1 Test_16 signal Source : NATURAL := 0; signal Destination_1 : NATURAL := 0; signal Destination_2 : NATURAL := 0; signal Destination_3 : NATURAL := 0; signal Destination_4 : NATURAL := 0; signal Clock : BIT := 0;第四

33、十九页，共九十一页。Guarded Signals In BlockBlockLabel: is Declarations; ConcurrentStatements; BlockLabel;第五十页，共九十一页。Guarded Signals Example (LT1.vhd)library ieee;use ieee.std_logic_1164.all; LT1 port ( D, CLK : in bit; Q : out bit; Free_in : in bit; Free_out : out bit ); LT1; LT1_archLT1 begin U1: Q = guarde

34、d D; Free_out = not Free_in; U1; LT1_arch; Q = D; Free_out = not Free_in;DCLKFree_inQFree_out第五十一页，共九十一页。Guarded Signals Example (LT.vhd)library ieee;use ieee.std_logic_1164.all; LT port ( D, CLK : in bit; Q : out bit; Free_in : in bit; Free_out : out bit ); LT; LT_archLT begin U1: Q = D; Free_out =

35、 not Free_in; U1; LT_arch; Q = D; Free_out = not Free_in;LatchDCLKFree_inQFree_out第五十二页，共九十一页。Guarded Signals Example (Wave)第五十三页，共九十一页。AgendanOverviewnEntitynKeywordsnBlocknSubprogramnFunctionnProcedurenLibrary & UsenPackage nConfiguration第五十四页，共九十一页。Process Definitionprocess_label: (sensitivity_li

36、st) is process_declarative_part process_statement_part process_label;第五十五页，共九十一页。Example of Process (Test_16.vhd) Blck_Test_1: (clock = 1 and ClockEVENT) Destination_1 = guarded Source;Destination_2 = Source; Blck_Test_1; Blck_Test_2: (Clock = 1 and not(ClockSTABLE) Destination_3 =guarded Source;Des

37、tination_4 =Source; Blck_Test_2;Monitor:variable Source_Var : NATURAL;variable Dest_1_Var, Dest_2_Var : NATURAL;variable Dest_3_Var, Dest_4_VAr : NATURAL Source_Var := Source;Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;wait on Des

38、tination_1,Destination_2, Destination_3,Destination_4; Monitor;Tick_Tock:wait for 10 ns;Clock =not clock; Tick_Tock; Source_Wave: Source =1 after 8 ns, 2 after 15 ns, 3 after 16 ns, 4 after 17 ns, 5 after 18 ns,6 after 19 ns; Behave_1; Test_16 Test_16;Behave_1 Test_16 signal Source : NATURAL := 0; s

39、ignal Destination_1 : NATURAL := 0; signal Destination_2 : NATURAL := 0; signal Destination_3 : NATURAL := 0; signal Destination_4 : NATURAL := 0; signal Clock : BIT := 0;第五十六页，共九十一页。Example of Process (Test_16.vhd zoom)Monitor:variable Source_Var : NATURAL;variable Dest_1_Var, Dest_2_Var : NATURAL;

40、variable Dest_3_Var, Dest_4_VAr : NATURAL Source_Var := Source;Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;wait on Destination_1,Destination_2, Destination_3,Destination_4; Monitor;Tick_Tock:wait for 10 ns;Clock =not clock; Tick_T

41、ock;第五十七页，共九十一页。Process Example With Sensitive Table (MY_DFF.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;-entity MY_DFF is port ( D, CP : in std_logic; Q : out std_logic );end MY_DFF; MY_DFF_arch MY_DFF if then Q = D; end if; MY_DFF_arch;

42、D Q CLK第五十八页，共九十一页。Process Example With Wait (MY_DFF.vhd) MY_DFF_arch MY_DFF Q = D; MY_DFF_arch;D Q CLK第五十九页，共九十一页。Process Example (Latch.vhd)library ieee;use ieee.std_logic_1164.all;-entity LT is port ( D, CLK : in bit; Q : out bit );end LT; LT_arch LT (CLK, D) if CLK = 1 then Q = D; end if; LT_arc

43、h;D Q CLKDCLKQ第六十页，共九十一页。Process (PROC2 Diagram) 脉冲生成器 PA 脉冲生成器 PB to_b to_a X 第六十一页，共九十一页。Process Example (Proc2.vhd)library ieee;use ieee.std_logic_1164.all;-entity PROC2 is port ( X: in std_logic);end PROC2; PROC2_arch PROC2 signal to_a, to_b: std_logic := 0; PA: process(X, to_a) begin if (Xevent

44、 and X = 1) or (to_aevent and to_a = 1) then to_b = 1 after 20ns, 0 after 30ns; end if; end process PA; PB: process(to_b) begin if (to_bevent and to_b = 1) then to_a = 1 after 10ns, 0 after 20ns; end if; end process PB; PROC2_arch; PA: process(X, to_a) begin if (Xevent and X = 1) or (to_aevent and t

45、o_a = 1) then to_b = 1 after 20ns, 0 after 30ns; end if; end process PA;PB: process(to_b) begin if (to_bevent and to_b = 1) then to_a = 1 after 10ns, 0 after 20ns; end if; end process PB; 脉冲生成器脉冲生成器PA 脉冲生成器脉冲生成器PB to_b to_a X 第六十二页，共九十一页。Process Example (Proc2 Wave) 脉冲生成器PA 脉冲生成器PB to_b to_a X 第六十三页

46、，共九十一页。AgendanOverviewnEntitynKeywordsnBlocknProcessnProcedurenLibrary & UsenPackage nConfiguration第六十四页，共九十一页。Function Definition Name (ParamList) Type; Name (ParamList) Type DeclarativePart; StatementPart; Name;DeclarationBody第六十五页，共九十一页。Functions Example (My_Package.vhd)library ieee;use ieee.std_

47、logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- my_package my_package; (S1, S2: in std_logic_vector) std_logic_vector; my_package my_package; (S1, S2: in std_logic_vector) std_logic_vector variable tmp: std_logic_vector(S1range); tmp := S1+S2; return tmp; ;第六十六页，共九十一页。F

48、unction Call Examplelibrary ieee;use ieee.std_logic_1164.all;library work;use work.my_package.all;-entity SUBPROC is port ( X : in std_logic_vector(3 downto 0); Y : in std_logic_vector(3 downto 0); Z : out std_logic_vector(3 downto 0) );end SUBPROC; SUBPROC_arch SUBPROC Z = SUBPROC_arch;XYZ第六十七页，共九十

49、一页。AgendanOverviewnEntitynKeywordsnBlocknProcessnFunctionnLibrary & UsenPackage nConfiguration第六十八页，共九十一页。Procedure Definition Name (ParamList) Name (ParamList) DeclarativePart; StatementPart; Name;DeclarationBody第六十九页，共九十一页。Procedure Example (My_Pachage.vhd)library ieee;use ieee.std_logic_1164.all;

50、use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- my_package my_package; my_package my_package; (A : in std_logic C : out std_logic);(A: in std_logic; B: out std_logic) B := not A; 第七十页，共九十一页。Procedure Call Examplelibrary ieee;use ieee.std_logic_1164.all;library work;use work.my_package