用vhdl语言设计计数器.doc

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1、【精品文档】如有侵权，请联系网站删除，仅供学习与交流用vhdl语言设计计数器.精品文档.76进制计数器LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU_76 IS PORT (CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END CDU_76; ARCHITECTURE AA OF CDU_76 IS SIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

2、PROCESS(CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN IF(COUT2=7 AND COUT1=5) THEN COUT2=0000;COUT1=0000; ELSE IF (COUT1=9) THEN COUT2=COUT2+1;COUT1=0000; ELSE COUT2=COUT2;COUT1=COUT1+1; END IF; END IF; END IF; END PROCESS; Q=COUT2&COUT1; END AA;24进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD

3、_LOGIC_UNSIGNED.ALL;ENTITY CDU_24 ISPORT (CLK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CDU_24;ARCHITECTURE AA OF CDU_24 ISSIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF (CLKEVENT AND CLK=1) THEN IF(COUT2=2 AND COUT1=3) THEN COUT2=0000;COUT1=0000; ELSE IF (COUT1=9) THEN COUT2=COUT2+1;COUT1=0000; ELSE COUT2=COUT2;COUT1=COUT1+1; END IF; END IF;END IF;END PROCESS;Q0); ELSIF CLKEVENT AND CLK=1 THENIF SET=0 THEN CQI:=(OTHERS=1); ELSIF EN=1 THEN IF CQI0); END IF; END IF; END IF; IF CQI=9 THEN COUT=1; ELSE COUT=0; END IF; CQ=CQI; END PROCESS;END behav;