最新SoC设计方法与实现第十四章 IO环设计2(共20张PPT课件).pptx
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1、SoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬第十四章第十四章I/O设计设计(shj)及封装及封装(二)(二)第一页,共二十页。 OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O ring designPackage Selection第二页,共二十页。Package FunctionsSignal distributionPower distributionHeat dissipationCircuit support and protection from envi
2、ronmentA space transformer between the fine pitch grid of IC and the PCB (Printed Circuit Board) pitch grid第三页,共二十页。SingulationMoldingSolder Ball AttachPackaging Process SawingWire BondingDieDie AttachWaferWireSubstratePackingFinal TestSolder BallMolding Compound第四页,共二十页。Typical IC PackageBall Grid
3、Array (BGA)Small Outline PackageDual-In-Line PackagePlastic Pin Grid ArrayPlastic Quad Flat PackageChip Scale Package (CSP)System In Package (SIP)Plastic Leaded Chip CarrierThin Outline Package第五页,共二十页。Industry Packing Trends第六页,共二十页。Ball Grid Array (BGA) BGA is a die-up design, plastic over-molded
4、BGA using 2-4 layer BT substrate 第七页,共二十页。More Advantage of BGAImproved electrical performance due to shorter distance between the chip and the solder ballsImproved thermal performance by use of thermal vias, or heat dissipation through power and ground plane incorporated in the substrateReduced han
5、dling-related lead damages due to use of solder balls instead of metal leadsWhen reflow attached to boards, the solder balls self align leading to higher manufacturing yields第八页,共二十页。Flip Chip PackagesPros Good electrical performance(reduced inductance) Good thermal performance w/heat sink Large num
6、ber of die pads per die areaSmall die size and low package heightCons High cost solution Board level reliability concernsDirect solder bumping onto the die, placing the interconnection bump directly onto the substrate, eliminating the need for wire bonding. SUBSTRATE(Organic or Ceramic)CHIPSolder bu
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