华南理工大学2013年数字系统设计(全英)试题A卷.doc

^` 姓名 学号 学院 专业 座位号 ( 密 封 线 内 不 答 题 ) ……………………………………………………密………………………………………………封………………………………………线……………………………………线……………………………………… _____________ ________ … 诚信应考,考试作弊将带来严重后果！ 华南理工大学期末考试 《数字系统设计（全英课）》试卷A （2014.1.16） 注意事项：1. 考前请将密封线内各项信息填写清楚； 2. 所有答案请在试卷上答题； 3．考试形式：闭卷； 4. 本试卷共 三 大题，满分100分， 考试时间120分钟。 题 号 一 二 三 总分 得 分 评卷人 1. Multiple choice test（2ⅹ10=20 marks） 1 . Which of the following statements is not true? （ D ） A． VHDL signal assignment needs a time delay to take effect B． VHDL signal can be declared in architecture, it’s global C． VHDL variable assignment takes effect immediately D． VHDL variable is usually declared in process, it should be included in sensitivity list 2. Which of the following VHDL data types can be used directly， without explicit declaration? （ C ） A. STD_LOGIC ；B. STD_LOGIC_VECTOR；C. BIT；D. ARRAY 3. Which of the following statements on PLD is not true （ B ） A. CycloneII is produced by Altera B. FPGA is based on product terms C. FPGA is field programmable gate array 4. Which of the following statements on sequential circuit is true（ B） A. In synchronous circuit，the actions of Flip-Flops are not necessarily synchronized by the same clock signal B. In asynchronous circuit， the states of Flip-Flops don’t change simultaneously C. The input change of Moore state machine is directly reflected by output 5. Which of the following statements on state machine description is not true ( C ) A．In one-process description style, output can be synchronized B. Two-process description style can avoid unwanted registers C. Two-process description style consumes more resources than one-process description 6. Which of the following statements on metastability is true ( B ) A. In sequential circuit, metastability doesn’t occur if either the set-up time requirement or the holding time requirement is met. B. Metastability doesn’t negatively impact the system if the metastable output resolves to the normal state before it is captured by the next register. C. Metastability usually occurs in synchronous circuit. 7. Which of the following statements on VHDL signal is not true（ C ） A . VHDL signal is usually synthesized as node or wire. B. In VHDL entity, port is considered as signal by default C. Assignment to the same signal in different processes can be synthesized, but only one signal assignment takes effect. 8. For state encoding in state machine, which of the following scheme is more simple for decoding at the prices of more Flip-Flops in encoding: ( A) A. one hot code B. Natural binary code C.Gray code 9. Which of the following statements on VHDL case statement is not true（ B ） A. Each branch of case statement should be corresponding to one or several possible values of the evaluated expression. B. Statement “WHEN OTHERS=>NULL” must be included in case statement C. In execution of case statement，only one branch is selected 10. Which of the following statements is not concurrent ?（ B ） A. process statement B.CASE statement C. component instantiation D.WHEN…ELSE…statement 2. Short answer questions（ 5ⅹ4=20 marks） 1、Please specify the basic components of ASM chart, particularly, explain what a state is. Basic components of ASM chart: state box, decision box, and conditional output box. One state is more than a state box, conditional output box, or decision box can also be a part of the state. A state represents the system state during one clock cycle, indicating the operations to be done in the state. 2、What is the difference between sequential logic circuit and combinational logic circuit? Combinational circuit: changes in inputs are immediately reflected by changes in output. The stable output depends on the current input only. The outputs of a system depend on past values of its inputs as well as the present state values.(depend on both present state and history state) 3、Please specify the basic structure of sequential logic circuit Structure: it is composed of combinational logic gates, and memory components such as Flip-flop, registers. 4、Please describe the concept of set-up time and holding time. Set up time： To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edge (register setup time or tSU). if the time is not long enough, reliable operation can not be guaranteed. Hold time： To ensure reliable operation, the input to a register must be stable for a minimum time after the clock edge (register hold time or tH). if the time is not long enough, reliable operation can not be guaranteed. 3、Comprehension & design ( 60 marks) 1、Using VHDL, Please describe a tri-state multiplexer (MUX) according to the following requirements: （10 marks） input output oe a b sel y 1 a b 0 a 1 b 0 - ‘Z’ LIBRARY IEEE； USE IEEE.std_logic_1164.ALL; ENTITY MUX IS PORT(oe, a, b, sel: in std_logic; y: out std_logic); END MUX; ARCHITECTURE BEHAV OF MUX IS BEGIN PROCESS(oe,a,b,sel) BEGIN If oe=’1’ then if sel=’0’ then y<=a; else y<=b; end if; else y<=’Z’; end if; END PROCESS: END ARCHITECTURE; 2、As a part of testbench, please describe the following stimuli （6 marks） … Signal S1：std_logic; Signal S2：std_logic; … Process Begin S1<=’0’; Wait for 10 ns; S1<=’1’; Wait for 5 ns; S1<=’0’; Wait for 10 ns; End process; Process Begin S1<=’0’; Wait for 5 ns; S1<=’1’; Wait for 15 ns; S1<=’0’; Wait for 5 ns; End process; 3、Please draw the RTL diagram for the following VHDL codes（5 marks） entity var_sig is port(data : in bit_vector (1 downto 0) ; clk : in bit; z : out bit); constant k1 : bit_vector := “01”; constant k2 : bit_vector := “10”; end var_sig; architecture A of var_sig is begin var : process variable a1 , a2 :bit_vector (1 downto 0); variable a3 : bit; begin wait until clk = ‘1’ and clk’ event ; a1 := data and k1; a2 := data and k2; a3 := a1(0) or a2(1); z <= a3; end process var; end A 4、Please complete the waveforms according to the following VHDL codes（6 marks） Library ieee; Use ieee.std_logic_1164.all; Entity D_latch is port ( D, Enable: in std_logic ; Q1，Q2: out std_logic ); End D_latch; Architecture behav of D_latch is Begin process(D, Enable) begin if (Enable=‘1’) then Q1<=D; end if; end process; process(Enable) begin if (Enable=‘1’) then Q2<=D; end if; end process; End behav; 5、Design a 4-bit ALU (Arithmetic Logic Unit), which can complete the following operations on 4-bit inputs a and b: 1) Mode 1: Addition (a +b) Mode 2: OR (a or b) Mode 3: AND (a and b) Mode 4: XOR (a xor b) 2) The working mode of the ALU depends on the mode input M0 and M1. For example: M0M1 MODE 00 addition 01 OR 10 AND 11 XOR 3) The addition operation should have carried-in bit and carried-out bit Questions: (13 marks) 1. Please indicate the inputs and outputs of the ALU Inputs: a, b, M0,M1,ci Ouput: s, co 2. Please finish VHDL design of ALU， including entity and architecture description. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; Entity ALU is port ( a, b :in std_logic_vector(3 downto 0); m0, m1, ci: in std_logic; s: out std_logic_vector(3 downto 0); co: in std_logic;); end ALU; architecture behav of ALU is signal mode : std_logic_vector(1 downto 0); begin mode<=m1&m0; process variable temp1, temp2, temp3: std_logic_vector(4 downto 0); begin if mode=”00” then temp1:=0&a; temp2:=0&b; temp3:= temp1+ temp2+ci; co=temp3(4); s<=temp3(3 downto 0); elsif mode=”01” then s<=a or b; elsif mode=”10” then s<=a and b; elsif mode=” 11” then s<=a xor b; else s<=”ZZZZ”; co<=’Z’; end if; end process; end architecture; 6. Please read each piece of the following codes carefully. Does each of them have the same circuit behavior like the following circuit diagram? If no, please give the reasons. (9 marks) （a） process begin wait until rising_edge(clk); d <= not c; c <= a and b; end process; (b) process begin wait until rising_edge(clk); c1 <= a and b; c2 <= not c1; d <= c2; end process; (c) process begin wait until rising_edge(clk); c1 <= a and b; d <= c2; end process; process (c1) begin c2 <= not c1; end process; (a) yes: (b) no: extra register is introduced. (c) yes 7、Design a serial data transmitter (串行数据发送器)。 Parallel data input ‘Z’ of 8 bits is loaded firstly in the transmitter, and serially transmitted through port ‘X’. The detailed requirements are listed as follows: a) Input signal ‘load’ is used for parallel data loading. If load=’1’, parallel data input ‘Z’ is loaded in the serial transmitter, and output signal ‘empty’=’0’ to turn off the LED; b) Least significant bit (最低位) is transmitted firstly; c) A start bit of logic ‘0’ (起始位 0) is transmitted firstly before the 8-bit real data transmission; d)A parity bit (奇偶效验位) and stop bit of logic ‘1’ (停止位 1)are transmitted after the 8 –bit real data transmission; e) After the transmission of the stop bit, output signal ‘empty’=’1’ to turn on the LED; Question: (11 marks) 1. Please specify the port information. Input : Output: 2.Please draw an ASM chart for the serial transmitter.