altera原版文章：数字预矫正Digital Predistortion.ppt

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1、altera原版文章：数字原版文章：数字预矫正预矫正Digital Predistortion 2002AgendanIntroductionnAlgorithm- Standard lookup table method- Phase related errors- Memory effectnImplementation- Multipliers- Memory- Cordic- Processors 2002Introduction: Purpose nTechnology demonstrator- Show DPD can be done efficiently on PLD- Pr

2、ovide starting point for design- Show efficient implementation of key components- Provide FPGA benchmark for customer design 2002Introduction: PredistortionVRFVinVRFVinOverall LinearResponseVrf = kVinVRFVinPAVrf = kVinIdeal PAVdVPAPAVrf = fnlkVdReal PADPDVd = 1/fnlVinVdVinPredistorter 2002Algorithms

3、: OverviewnAdaptive Lookup Table (LUT)- Lookup table for phase and magnitude correction values- Deals with magnitude dependent errorsnVolterra modelling of PA- Direct implementation- Indirect LUT implementation 2002Algorithm: Distance Gradient MethodnAssumption: Error only depends on magnitude arcta

4、n(I/Q)LUT(r & )I & QDemodaddressr(I2 +Q2)1/2 arctan(I/Q)r(I2 +Q2)1/2delaydelayQr*cos()Ir*sin()I & QmodPAI,Q inI,Q out(-1)(-1) 2002Algorithm: Distance Gradient Method MATLAB simulation results using SALEH PA model EVM improved in region of 90% 2002Dist Gradient LUT Freq Plotsn Predistortion improves

5、ACLR by 70dB(considering 700-900 and 1100-1300 as side-band regions for measurements)n Simplified simulation environment(using SALEH PA model) 2002Algorithm: Phase related error0102030405060700.90.9511.051.11.15addr(magn)magnitude correction010203040506070-0.8-0.6-0.4-0.20LUT contentaddr(magn)phase

6、correctionnAdds dimension to lookup tablenIncreases memory, logic same size as beforenIncreases time to convergeLUT content, LUT content,Without phase error compensation With phase error compensation 2002Algorithm: Memory effectnModels effect of short term temperature increase on siliconnThree possi

7、ble approaches- Add “delta look-up table” (Intersil solution)- Add new dimension to LUT (fully adaptive)- Use FIR in magnitude address calculation 2002Algorithm: Memory effectnPA models:- Saleh 1lMemoryless, lErrors only dependent on input magnitude- Volterra based, lwith or without memory: 2,3lErro

8、r depend on input magnitude and phase1 A. Saleh and J.Salz, Adaptive Linearization of Power Amplifiers in Digital Radio Systems, Bell Syst. Tech. J., Vol.62, No. 4, pp 1019-1033, Apr. 19832 L.Ding, G.T.Zhou, D.R.Morgan, Z.Ma, J.S.Kenney, J.Kirn and C.R.Giardina, Memory polynomial predistorter based

9、on the indirect learning architecture, Proc.IEEE Global Telecommunications Conference, Taipei, Taiwan, Nov.20023. H. Qian, and G.T. Zhou, A neural network predistorter for nonlinear power amplifiers with memory, Proc. 10th IEEE DSP Workshop (DSP2002), Pine Mountain, GA, October 2002 2002Algorithm: M

10、emory effectnError mechanism: - Error depends on temperature- Temperature depends on previous magnitudesnNew PA model:- Altera modellError depends on current and previous magnitudes lError independent of input phasenSolution - FIR filter in address calculation 2002 arctan(I/Q)LUT(I & Q)I & Q Demodad

11、dressr(I2 +Q2)1/2 arctan(I/Q)r(I2 +Q2)1/2delayI = r*sin()Q = r*cos()I & QmodPAI,Q inI,Q out(-1)(-1)delayFIRProcessor + hardware accelerationPredistortion Reference DesignDSP BlocksSyncNCOFIR 2002DSP Block Architecture & Resources+Optional PipeliningOutput RegistersOutput MUX+ - S S+ - S SInput Regis

12、tersnHigh Performance DSP Operation-18x18 Functions at 282 MHznInput, Output & Pipelining registers-Reduce overall Logic usagenAdd/Accumulate/Subtract-Signed & unsigned operations-Dynamically change between Add & Subtractn Support complex multiplications- (Ar + jAi) x (Br + jBi) = (Ar Br AiBi) + j(A

13、i Br + ArBi)- 4 Multiplications, 1 Addition & 1 Subtraction - + 2002 arctan(I/Q)LUT(I & Q)I & Q Demodaddressr(I2 +Q2)1/2 arctan(I/Q)r(I2 +Q2)1/2delayI = r*sin()Q = r*cos()I & QmodPAI,Q inI,Q out(-1)(-1)delayFIRProcessor + hardware accelerationPredistortion Reference DesignDSP BlocksRAMSyncNCOFIR 200

14、2TriMatrix MemorynTodays applications need more high performance memorynOne size does not fit all nWide choice of modes and widthsM512 BlocksM4K BlocksM-RAMExternal Memory DevicesnDDR SDRAM & SRAMnSDR SDRAMnQDR & QDRII SRAMnZBT SRAMnDDR FCRAMnTrue Dual Port RAM nEmbedded Shift Register Moden512K bit

15、s nOperates Up to 300MhznTrue Dual Port RAM nEmbedded Shift Register ModenOperates Up to 312MhznRate ChangingnEmbedded Shift Register ModenOperates Up to 312MhzMore Bits For Larger Memory BufferingMore Data Ports for Greater Memory Bandwidth 2002 arctan(I/Q)LUT(I & Q)I & Q Demodaddressr(I2 +Q2)1/2 a

16、rctan(I/Q)r(I2 +Q2)1/2delayI = r*sin()Q = r*cos()I & QmodPAI,Q inI,Q out(-1)(-1)delayFIRProcessor + hardware accelerationPredistortion Reference DesignDSP BlocksRAMCORDICSyncNCOFIR 2002CORDICnHardware efficient algorithm for computing functions such as:- Trigonometric- Hyperbolic- LogarithmicnIterat

17、ive solution that uses only shifts and adding/subtracting- High performance as no multiplications and divisions- Simple/less hardware required 2002Altera CORDIC solution for DPDCORDICX_inY_inZ_inmodeX_outY_outZ_out Cartesian to Polar conversion X_in, Y_in = Cartesian values, Z_in=0, mode = 0 X_out =

18、 magnitude, Z_out = phase Polar to Cartesian conversionX_in = magnitude, Z_in=phase, Y_in=0, mode = 1X_out, Y_out = Cartesian values Mode selects conversion direction Pipelined enabling new inputs to be applied in every clk cycle After initial latency valid outputs will appear on every clk cycle Tim

19、esharing : on each clk cycle the mode of the CORDIC can be changed 2002CORDIC ArchitectureQuadrant detect & IP modifyAdd/Sub &ShiftRegQuadrant AdjustIteration 1Iteration n Parallel Architecture enabling high performance CORDIC algorithm can only deal with vector rotations of 90 to +90 degrees Requir

20、e additional logic (Quadrant blocks) to be able to deal with vectors in any of the four quadrants Parameterisable code input vector widths and number of iterations can be changed. 2002CORDIC ImplementationnLEs in Altera PLDs- Each LE is suited for implementing the required adders/subtractors.- LEs c

21、an dynamically change from operating as an adder to subtractor- Each LE contains a register nPerformanceVector WidthsIterationsFmaxLEs requiredAbs no. % of total in 1S101616219MHz130012%3232189MHz460043% 2002 arctan(I/Q)LUT(I & Q)I & Q Demodaddressr(I2 +Q2)1/2 arctan(I/Q)r(I2 +Q2)1/2delayI = r*sin()

22、Q = r*cos()I & QmodPAI,Q inI,Q out(-1)(-1)delayFIRProcessor + hardware accelerationPredistortion Reference DesignDSP BlocksRAMCORDICSyncNCOFIR 2002Implementation: Processor?nShould we use processor?- ForlFlexibilitylEasy to add custom interpolation or similarlLow data rate in feedback path at base b

23、and- AgainstlStraightforward data path (few “IF” branches)lToo slow at IFlNo clear size advantagelDifficult to exploit deeply pipelined CORDIC 2002Performance (Dhrystone MIPS 2.1)20501002000Soft CoreHard Core Soft Core Advantages Flexibility Low Cost Portable Design Scalability Obsolescence Proof Fi

24、ts Broad Range of Altera PLD Families Hard Core Advantages High Performance 922TDMI Time-to-Market Lots of On-Chip Memory Leverage Large Existing Code BaseExcalibur Embedded Processor Cores 2002ImplementationnForward path: I,Q multipliersnLookup table: Dual port memorynFeedback path- Nios with custo

25、m instructions- CORDIC acceleration- Multiply acceleration 2002Target devicesnStratix - - Contains DSP Blocks- TriMatrix RAM allows for Large lookup tables (multiple dimensions)- Suitable if up/down converters are also integratednCyclone - - Extensive use of CORDIC- Lowest cost 2002Ref Design Resour

26、ce Utilisation Estimatesn5000 LEs (50% of avail in 1S10)n4 DSP blocks (67% of avail in 1S10)n3 M4K RAM blocks (5% of avail in 1S10)n2 M512 RAM blocks (2% of avail in 1S10)nAssumes 18bit wide I/Q, 64 deep X 32 bit wide LUT.nThe ref design only contains the adaptive lookup table algorithm. 2002SOPC 3.

27、0 Builder nBuild a Custom Companion Chip for Your Processor-Based System With SOPC Builder- Interface to Popular MicroprocessorslPowerPClTI DSPlPCI - Custom Peripheral ContentlCommunications IPlSignal Processing Algorithms lMemory Interfaces- Hardware Acceleration Functions lSecurity IPlImage Proces

28、singlTraffic Management / Routing Algorithms 2002SummarynReference design based on lookup tables on Stratix 1S10nWorks for memoryless PAnCompensates for memory effect- Assumption: Errors independent of phasenCan be tuned and modifiednOpen Source extract key components, leave the rest 2002 Discussion

29、 2002Development ToolsnQuartus II- Robust, stable tool for block-based design- Includes everything you need to build SOPC designs- Interfaces to all leading 3rd party EDA toolsnSOPC Builder- Configures processors, bus architectures, IP and firmware in one simple environment- Interfaces to Nios, XA f

30、amily & popular Microprocessor familiesnDSP Builder- Works with MATLAB/Simulink to provide an FPGA development environment that is ideal for systems engineers- Works with SOPC Builder to give a C-based DSP design flow 2002What Is DSP Builder?nInterface between Quartus II & Matlab/Simulink- Integrate

31、s Algorithm & Hardware DevelopmentnAltera Blockset- Library of Fixed-Point Simulink Functions/BlocksnSignalCompiler - Main DSP Builder Block- Converts Simulink Model Files to HDL 2002DSP Builder 2002Stratix DSP Development Board40-Pin Connectors for Analog Devices Texas Instruments Connectors on Und

32、erside of BoardMictor-Type Connectors for HP Logic AnalyzersMAX 7000 DeviceAnalog SMA ConnectorsD/A ConvertersA/D ConvertersPrototyping AreaNios Expansion Prototype Connector 20022000200220040.18u / 0.15u / 0.13uFmax = 60-120MHzMax Density = 70K LEEmbedded RAM = 1.2Mbit max.Transceiver = 1.25Gbps0.1

33、3uFmax = 80-175MHzMax Density = 100K LETri-Matrix Memory = 10Mbit max.Transceiver = 3.125GbpsPerformance90nm Fmax = 150-300 MHzMax Density = 170K LEMemory = 16Mbit max.Transceiver = 6.5Gbps 2002Wireless Solution UpdateAsif BatadaMarketing Manager, Wireless Business Unit 2002AgendanMobile Base-statio

34、n ArchitecturenBasics of Digital IF and Digital Predistortion LinearizernRF Card ArchitecturenPredistortion Linearizer ImplementationnConclusion 2002AntennaRNC I/FIP InterfaceSwitch ControllerA/DD/ABase Band SignalProcessingSwitch I/FHost Processor (CPU)Clock GeneratorPLD ApplicationControl BoardCha

35、nnel CardRNCDigital IFDigitalPredistortion LinearizerMux/De-MuxHostuPRF CardBase-Station ArchitectureLVDSw/CDRATMprocPALNA 2002AgendanMobile Base-station ArchitecturenBasics of Digital IF and Digital Predistortion LinearizernRF Card ArchitecturenPredistortion Linearizer ImplementationnConclusion 200

36、2Digital IF OpportunitynDigital IF is a high volume application for FPGA:- Macro BTS can be configured into two different ways:l2 carriers for 3 sectorsl1 carrier for 6 sectors- Each BTS hasDigital IF Implementation: 6 x EP1S20Predistortion Implementation: 6 x EP1S106 x EP1S20 + 6 x EP1S10 per BTS1

37、carrier(5Mhz for UMTS)6 Sector Cell603 SectorCell120 2002Traditional IF-Based TransmitternIssues with traditional transmitter- Not flexible to support multiple standards- Non-ideal local frequencies are source of noise- RF and analog components of radio are more difficult to manufacture and have hig

38、her reliability issues- Higher costBBfilterBBfilter+90f1IFfilterRFfilterf2AmpPAIQDACDAC 2002Digital IF Sym. MapperFIRfilterNCOSFIRfilterf2AmpPAIFfilterRFfilterDigital Up-ConverternWith the advancement of data converter technology (100Msps +), it is possible to sample at IF (intermediate frequency) a

39、nd do Channelization in Digital domainnAdvantages of Digital IF- Channel selection can be done in digital domain- Higher precision in frequency selection and shorter settling time of DDS- Good amplitude and phase balance - Extremely linear phase and very low shape factor of base-band filterDAC 2002P

40、redistortion LinearizernRF stage (transmitter) uses a linear Power Amplifier (PA) to boost the signalsnLinear PAs are very expensive- Some cases it makes up half the cost of BTSnNon-Linear PAs are cheaper- LDMOS based technology- LDMOS introduces distortion of its ownnPredistortion in digital domain

41、- Pre-distort the signal so that when it goes thru PA, the overall response is linear- Common technique Look-up Table based approachlStore the points on the transfer function in a look-up tablelOne of our customers evaluating 20K400E for this applicationlNios is well suitedInput PowerOutputPowerAdd

42、Predistortion 2002AgendanMobile Base-station ArchitecturenBasics of Digital IF and Digital Predistortion LinearizernRF Card ArchitecturenPredistortion Linearizer ImplementationnConclusion 2002RF Card 1st Generation DesignnCustomers have either designed their own Digital IF chip (w/o DPD) or are usin

43、g ASSP (mostly GrayChip)nLimitations with current implementation:- Custom Filter Specs Adj Channel Power Ratio (ACPR) Requirement Driven by Architecture- Decimation and Interpolation Ratios Driven by Standards and Internal implementationnNeed to add more carriers- Availability of Multi-Carrier Power

44、 Amplifier- Higher capacity channel cardsnHigher Data rates over the back plane 2002InterpolationInterpolationRRC FilterRRC Filter RRC FilterResamplerDecimationRRC FilterResamplerDecimationNCOQADCDACToAntFromAntTo ChannelCard(LVDS w/CDR)Input Fmt& Gain CntrlFromCh.Card(LVDS w/CDR) NCORF CardIIQDelay

45、MatchingTableAddressCalc(I2 +Q2)1/2LUT(I & Q)Compare &EstimateRSAdaptiveEst.I & QDemodFFTLoop Delay EstFromPA 2002AgendanMobile Base-station ArchitecturenBasics of Digital IF and Digital Predistortion LinearizernRF Card ArchitecturenPredistortion Linearizer ImplementationnConclusion 2002DelayMatchin

46、gLUT(I & Q)100 entries12 bit WordlengthTableAddressCalc(I2 +Q2)1/2IQCompare &EstimateRSI & QDemodulatorFFTAdaptive Est.Loop DelayEstimatorEmbedded ProcessorAltera MegaCore IPTo DUCIQ-IQAltera Solution for DPD 2002Optional FIFO, Memory, Other LogicNios ProcessorInteger Mult /Complex MultExampleALU On

47、lyALU + Intgr MultALU + Cmplx MultLoop Time (us)11.1900.5600.011Loop Clocks1119561.1MUL Clocks2533-Complex Mults per Second89K1.8M90.9MLoop Time = Execution of a single complex multiplyLoop Clocks = Number of clocks to execute single iterationMUL Clocks = Number of clocks to execute the MUL onlyCust

48、om Instruction ExampleHardware Acceleratorx 50 2002FlowAddressCalculationDDCFFTDelayMatching(.)_GainVerror= tan-1 (.)Sn+1=Sn-*escaleRn+1=Rn-*erotateI1Q1InQn.I1Q1InQn.I/P toDPDFromPAUpdateLUTLoop DelayMeasH/W AcceleratorCmplxMultProgrammableLogic ImplementationSoftware Implementation(Nios) 2002Interp

49、olationInterpolationRRC FilterRRC Filter RRC FilterDecimationRRC FilterResamplerDecimationNCOQToAntFromAntTo ChannelCard(LVDS w/CDR)Input Fmt& Gain CntrlFromCh.Card(LVDS w/CDR) NCORF Card Comprehensive SolutionIIQDelayMatchingTableAddressCalc(I2 +Q2)1/2LUT(I & Q)Compare &EstimateRSAdaptiveEst.I & QD

50、emodFFTLoop Delay EstFromPAArctanResamplerAltera MegaCore IPStratix Tri-MatrixStratix MAC BlockH/W Accelerator 2002Advantages of Using FPGAnGreater Flexibility- Filter specification based on ACPR requirements- Optimal filter architecture for most efficient implementation- Support multi-mode capabili