2022年多功能数字时钟VHDL源代码 .pdf

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1、源代码：Alert 模块：library ieee; use ieee.std_logic_1164.all; entity alert is port(dip:in std_logic_vector(3 downto 0); h1,h0,m1,m0,s1,s0:in std_logic_vector(3 downto 0);-输入秒、分高 /低位信号nao_h_h,nao_h_l,nao_m_h,nao_m_l:in std_logic_vector(3 downto 0); clk:in std_logic; q500,qlk,q1khz:out std_logic); end alert

2、; architecture behav of alert is begin process(clk) begin if clkevent and clk=1 then if m1=0101 and m0=1001 and s1=0101 then-当秒高位为5，低位为9 时且分高位为 5 if s0=0001 or s0=0011 or s0=0101 or s0=0111 then-当分的低位为1 或 3 或 5 或7 时q500=1;-低频输出为1 else q500=0;-否则输出为0 end if; end if; if m1=0101 and m0=1001 and s1=0101

3、 and s0=1001 then-当秒高位为5， 低位为 9时且分高位为5，-分低位为 9 时，也就是“ 59 分 59 秒”的时候“报时”qlk=1;- 高频输出为1 else qlk=0; end if; end if; end process; process(h1,h0,m1,m0,nao_h_h,nao_h_l,nao_m_h,nao_m_l) begin if dip(0)=1 and h1=nao_h_h and h0=nao_h_l and m1=nao_m_h and m0=nao_m_l then q1khz=1; else q1khz=0; end if; end pr

4、ocess; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 13 页 - - - - - - - - - end behav; braz模块：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity braz is port( dip:in std_logic_vector(3 downto 0); q5

5、00,qlk,q1khz:in std_logic; f1khz,f500hz:in std_logic; braz:out std_logic); end entity; architecture behave of braz is begin process(q500,qlk,dip) begin if dip=0010 or dip=1110 or dip=1010 or dip=0110 then braz=1; end if; if q500=1 then braz=f500hz; elsif qlk=1 or q1khz=1 then braz=f1khz; else braz0)

6、;tens:=(others=0);full=1; elsif (ones=1010) then tens:=tens+1;ones:=0000;full=0; end if; end if; one=ones; ten=tens; end process; end behave; 显示模块：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity display is port (clk:in std_logic; a,b,c

7、,d:in std_logic_vector(3 downto 0); mux_out:out std_logic_vector(3 downto 0); wei1,wei2,wei3,wei4:out std_logic); end display; architecture behave of display is signal sel:integer range 0 to 3; begin process(a,b,c,d,clk) begin if rising_edge(clk) then selmux_out=a; wei4=0;wei3=1;wei2=1;wei1mux_out=b

8、; wei4=1;wei3=0;wei2=1;wei1mux_out=c; wei4=1;wei3=1;wei2=0;wei1mux_out=d; wei4=1;wei3=1;wei2=1;wei1mux_out=1100; end case; end if; end process; end behave; 消抖模块：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debounce is port(key:in std_logic_vector(3 downto 0); cl

9、k:in std_logic; key_valid:out std_logic); end debounce; architecture behave of debounce is begin process(clk,key) variable cnt:integer range 0 to 31; begin if (key=0111 or key=1011 or key=1101 or key=1110)then if(clkevent and clk=1) then if cnt=31 then key_valid=1;-key pressed else key_valid=0;-no k

10、ey pressed cnt:=cnt+1;-cnt plus one end if; end if; else cnt:=0;-no key pressed,the conter reset key_valid=23) then nao_h=0; else nao_h=59) then nao_m =0; else nao_m nao_h_one nao_h_one nao_h_one nao_h_one nao_h_one nao_h_one nao_h_one nao_h_one nao_h_one nao_h_onenao_h_one nao_h_ten nao_h_ten nao_h

11、_tennao_h_ten nao_m_one nao_m_one nao_m_one nao_m_one nao_m_one nao_m_one nao_m_one nao_m_one nao_m_one nao_m_onenao_m_one nao_m_ten nao_m_ten nao_m_ten nao_m_ten nao_m_ten nao_m_tennao_m_teneighteighteighteighteighteighteighteighteighteighteight=11111111; end case; end process; end behave; 分频模块：lib

12、rary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned; entity fenpin is port(clk:in std_logic; f1khz:out std_logic); end fenpin; architecture behav of fenpin is signal mid:std_logic; begin 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 7 页，共 13 页 - - -

13、- - - - - - process(clk) variable cnum:integer range 0 to 25000; begin if (clkevent and clk=1) then cnum:=cnum+1; if cnum=25000 then mid = not mid; cnum:=0; end if; f1khz=mid; end if; end process; end behav; 1000 分频模块：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ie

14、ee.std_logic_arith.all; entity div1000 is port (clk:in std_logic; f1hz:out std_logic); end entity; architecture behav of div1000 is signal count:integer range 0 to 1000; begin process(clk) begin if rising_edge(clk) then count=count+1; if count=1000 then f1hz=1; else f1hz=0; end if; end if; end proce

15、ss; end behav; 分计数模块：library ieee; use ieee.std_logic_1164.all; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 8 页，共 13 页 - - - - - - - - - use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mincount is port(carry:in std_logic; key_valid:in std_log

16、ic; key:in std_logic_vector(3 downto 0); ten :out std_logic_vector(3 downto 0); one :out std_logic_vector(3 downto 0); full: out std_logic); end mincount; architecture behave of mincount is signal min:integer range 0 to 59; signal min_temp:integer range 0 to 59; signal min_temp1:integer range 0 to 5

17、9; begin process(carry) begin if rising_edge(carry) then min_temp=min_temp+1; if(min_temp=59) then full=1; min_temp=0; else full=0; end if; end if; end process; process(key,key_valid) begin if rising_edge(key_valid) then if (key=1101) then min_temp1=59) then min_temp1 =0; end if; end if; end if; end

18、 process; process(min) begin min one one one one one one one one one oneone ten ten ten ten ten tenten=1110; end case; end process; end behave; 小时计数模块：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity hcount is port( carry:in std_logic;

19、key:in std_logic_vector(3 downto 0); key_valid:in std_logic; ten :out std_logic_vector(3 downto 0); one :out std_logic_vector(3 downto 0); end hcount; architecture behave of hcount is signal min_temp:integer range 0 to 23; signal min_temp2 :integer range 0 to 23; signal min:integer range 0 to 23; be

20、gin process(carry) 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 10 页，共 13 页 - - - - - - - - - begin if rising_edge(carry) then min_temp2=min_temp2+1; if(min_temp2=23) then min_temp2=0; end if; end if; min=23) then min_temp =0; else min_temp one one one one one one

21、one one one oneone ten ten tenten=1110; end case; end process; end behave; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 11 页，共 13 页 - - - - - - - - - 模式转换模块：library ieee; use ieee.std_logic_1164.all; entity modem is port(dip:in std_logic_vector (3 downto 0); hourH,

22、hourL,minH,minL,secH,secL:in std_logic_vector (3 downto 0); nao_h_h,nao_h_l,nao_m_h,nao_m_l:in std_logic_vector (3 downto 0); out4,out3,out2,out1:out std_logic_vector (3 downto 0); end modem; architecture behave of modem is signal mode:std_logic; signal mode_nao:std_logic; begin process(dip) begin i

23、f dip(2)=0 then mode_nao=1; elsif dip(3)=0 then mode=1; else mode_nao=0;mode=0; end if; end process; process(mode) begin if (mode_nao=1)then out4=nao_h_h; out3=nao_h_l; out2=nao_m_h; out1=nao_m_l; elsif mode=1 then out4=hourH; out3=hourL; out2=minH; out1=minL; else out4=minH; out3=minL; out2=secH; o

24、ut1=secL; end if; end process; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 12 页，共 13 页 - - - - - - - - - end behave; 500 分频模块 : library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity fz500Hz is port (clk:in

25、 std_logic; f500hz:out std_logic); end entity; architecture behav of fz500Hz is signal count:integer range 0 to 1; begin process(clk) begin if rising_edge(clk) then count=count+1; if count=1 then f500hz=1; else f500hz=0; end if; end if; end process; end behav; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 13 页，共 13 页 - - - - - - - - -