8051单片机硬件简介毕业论文外文翻译.docx

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1、一、英文原文The HardwareOverviewThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded ontrol systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eigh

2、t bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Sie- mens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog

3、 timers, and pulse width modulated outputs.Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available.This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a companys entire line of product

4、s since it can perform many functions and developers will only have to earn this one platform.The basic architecture consists of the following features:1、an eight bit ALU2、32 descrete I/O pins (4 groups of 8) which can be individually accessed3、two 16 bit timer/counters 4、full duplex UART.5、6 interr

5、upt sources with 2 priority levels.6、128 bytes of on board RAM.7、separate 64K byte address spaces for DATA and CODE memory.One 8051 processor cycle consists of twelve oscillator periods.Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and

6、samples of the interrupt daisy chain for pending interrupts.The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question.Therefore, if you have a sy

7、stem which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12.This gives aninstruction frequency of 921583 instructions per second.Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).Memory O

8、rganizationThe 8051 architecture provides the user with three physically distinct memory spaces which can be seen in Figure A - 1. Each memory space consists of contiguous addresses from 0 to the maximum size, in bytes, of the memory space. Address overlaps are resolved by utilizing instructions whi

9、ch refer specifically to a given address space. The three memory spaces function as described below.Figure A - 1 - 8051 Memory ArchitectureThe CODE SpaceThe first memory space is the CODE segment in which the executable program resides.This segment can be up to 64K (since it is addressed by 16 addre

10、ss lines) .The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM.However, this does not mean that the CODE segment must be implemented using an EPROM.Many embedded systems these days are using EEPROM which allows the memory to

11、 be overwritten either by the 8051 itself or by an external device.This makes upgrades to the product easy to do since new software can be downloaded into the EEPROM rather than having to sassemble it and install a new EPROM. Additionally, battery backed SRAMs can be used in place of an EPROM. This

12、method offers the same capability to upload new software to the unit as does an EEPROM, and does not have any sort of read/write cycle limitations such as an EEPROM has. However, when the battery supplying the RAM eventually dies, so does the software in it.Using an SRAM in place of an EPROM in deve

13、lopment systems allows for rapid downloading of new code into the target system.When this can be done, it helps avoid the cycle of programming /testing /erasing with EPROMs, and can also help avoid hassles over an in circuit emulator which is usually a rare commodity.In addition to executable code,

14、it is common practice with the 8051 to store fixed lookup tables in the CODE segment. To facilitate this, the 8051 provides instructions which allow rapid access to tables via the data pointer (DPTR) or the program counter with an offset into the table optionally provided by the accumulator.This mea

15、ns that oftentimes, a tables base address can be loaded in DPTR and the element of the table to access can be held in the accumulator.The addition is performed by the 8051 during the execution of the instruction which can save many cycles depending on the situation. The DATA SpaceThe second memory s

16、pace is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052.This segment is typically referred to as the DATA segment.The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than acce

17、ss to the XDATA segment because memory is addressed directly rather than via a memory pointer such as DPTR which must first be initialized.Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment. Such allocation must be done with care, however, d

18、ue to the limited amount of memory in this segment.Variables stored in the DATA segment can also be accessed indirectly via R0 or R1.The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles

19、depending on the source/destination data byte.The DATA segment contains two smaller segments of interest.The first subsegment consists of the four sets of register banks which compose the first 32 bytes of RAM.The 8051 can use any of these four groups of eight bytes as its default register bank.The

20、selection of register banks is changeable at any time via the RS1 and the RS0 bits in the Processor Status Word (PSW).These two bits combine into a number from 0 to 3 (with RS1 being the most significant bit) which indicates the register bank to be used. Register bank switching allows not only for q

21、uick parameter passing, but also opens the door for simplifying task switching on the 8051.The second sub-segment in the DATA space is a bit addressable segment in which each bit can be individually accessed.This segment is referred to as the BDATA segment.The bit addressable segment consists of 16

22、bytes (128 bits) above the four register banks in memory. The 8051 contains several single bit instructions which are often very useful in control applications and aid in replacing external combinatorial logic with software in the 8051 thus reducing parts count on the target system. It should be not

23、ed that these 16 bytes can also be accessed on a byte-wide basis just like any other byte in the DATA space.Special Function RegistersControl registers for the interrupt system and the peripherals on the 8051 are contained in internal RAM at locations 80 hex and above. These registers are referred t

24、o as special function registers (or SFRs for short).Many of them are bit addressable.The bits in the bit addressable SFRs can either be accessed by name, index or bit address. Thus, you can refer to the EA bit of the Interrupt Enable SFR as EA, IE.7, or 0AFH.The SFR scontrol things such as the funct

25、ion of the timer/counters,the UART, and the interrupt sources as well as their priorities.These registers are accessed by the same set of instructionsas the bytes and bits in the DATA segment. A memory map of the SFRs indicating the registers which are bit addressable is shown in Table A - 1.Denotes

26、 bit addressable Special Function Registers in this table and all following diagramsTable A 1The IDATA SpaceCertain 8051 family members such as the 8052 contain an additional 128 bytes of internal RAM which reside at RAM locations 80 hex and above. This segment of RAM is typically referred to as the

27、 IDATA segment. Because the IDATA addresses and the SFR addresses overlap, address conflicts between IDATA RAM and the SFRs are resolved by the type of memory access being performed, since the IDATA segment can only be accessed via indirect addressing modes.The XDATA SpaceThe final 8051 memory space

28、 is 64K in length and is addressed by the same 16 address lines as the CODE segment. This space is typically referred to as the external data memory space (or the XDATA segment for short).This segment usually consists of some sort of RAM (usually an SRAM) and the I/O devices or external peripherals

29、to which the 8051 must interface via its bus. Read or write operations to this segment take a minimum of two processor cycles and are performed using either DPTR, R0, or R1. In the case of DPTR, it usually takes two processor cycles or more to load the desired address in addition to the two cycles r

30、equired to perform the read or write operation. Similarly, loading R0 or R1 will take minimum of one cycle in addition to the two cycles imposed by the memory access itself. Therefore, it is easy to see that a typical operation with the XDATA segment will, in general, take a minimum of three process

31、or cycles. Because of this, the DATA segment is a very attractive place to store any frequently used variables.It is possible to fill this segment entirely with 64K of RAM if the 8051 does not need to perform any I/O with devices in its bus or if the designer wishes to cycle the RAM on and off when

32、I/O devices are being accessed via the bus. Bit processing and Boolean logicThe 8051 contains a single bit Boolean processor which can be used to perform logical operations on any of the 128 addressable bits in the BIT segment, the 128 addressable bits in the SFRs, and any of the 32 I/O lines (port

33、0 through port 3). The 8051 can perform OR, AND, XOR, complement, set, and clear operations on bits as well as moving bit values as one would normally move byte values.Listing A 1MOV C, 22H; move the bit value at address; 22H to the carry bitORL C, 23H; or the bit value at address; 23H into the carr

34、y bitANL 24H, C; and the carry bit into bit; address 24HThere are also conditional branches which use addressed bits as the condition.One such branch which is especially useful is the “jump if bit is set and clear bit” instruction.This branch and clear can be performed in two processor cycles and sa

35、ves a cycle or two over splitting the jump and the clear into two separate op codes. As an example, suppose that you had to write a routine which waited for pin P0.0 to set, but could not wait indefinitely.This routine would have to decrement a timeout value and exit the polling loop when this timeo

36、ut is exceeded.When pin P0.0 sets, the processor must force it back to 0 and exit the polling loop.With normal logic flow, the routine would look like the following.Listing A - 2MOVtimeout, #TO_VAL; set the timeout valueL2:JBP0.0, L1 ; check the bitDJNZtimeout, L2 ; decrement the timeout counter; an

37、d sample againL1:CLRP0.0 ; force P0.0 to logic level 0RET ; exit the routineAddressing ModesThe 8051 is capable of performing direct and indirect memory accesses on its various memory spaces. These are the typical methods through which processor systems access memory. Direct accesses are characteriz

38、ed by presence of the address of the accessed variable in the instruction itself. These accesses can only be performed on the DATA segment and the SFRs. Examples of direct memory accesses are shown below.ListingA-3 MOV A,03H ;move the value at address 03H to ;theaccumulator MOV 43H,22H ;movethevalue

39、ataddress22Hto;address43HMOV 02H,C ;movethevalueofthecarrybitto;bitaddress02H MOV 42H,#18 ;loadaddress42Hwiththevalue18 MOV 09H,SBUF ;loadthevalueinSBUFinto;address09HIndirect accesses involve another register (DPTR , PC, R0, or R1 on the 8051 ) which contains the address of the variable to be acces

40、sed.The instruction then refers to the pointing register rather than the address itself.This is how all accesses to CODE, IDATA, and XDATA segments are performed.The DATA segment may also be accessed in this manner. Bits in the BDATA segment can only be accessed directly.Indirect memory accesses are

41、 quite useful when a block of data must be moved, altered or operated on with a minimum amount of code since the pointer can be incremented through the memory area via a looping mechanism.Indirect accesses to the CODE segment can have a base address in either the DPTR or the PC register and an offse

42、t in the accumulator.This is useful for operations involving lookup tables. Power ControlThe CHMOS versions of the 8051 feature two power saving modes that can be activated by software: idle mode and power down mode. These modes are accessed via the PCON (Power CONtrol) SFR which is shown in Table A

43、 - 2. The idle mode is activated by setting the IDLE bit high. The idle mode causes all program execution to stop. Internal RAM contents are preserved and the oscillator continues to run but is blocked from the CPU. The timers and the UART continue to function as normal. Idle mode is terminated by t

44、he activation of any interrupt. Upon completion of the interrupt service routine, execution will continue from the instruction following the instruction which set the IDLE bit.Interrupts on the 8051The basic 8051 supports six interrupt sources:two external interrupts, two timer/counter interrupts, a

45、nd aserial byte in/out interrupt.These interrupt sources force the processor to vector to one of five locationsin the lowest part of the CODE address space (serial input and serial output interrupts share the samevector).The interrupt service routine must either reside there or be branched to from t

46、here.A map of the interrupt vector for the 8051/8052 is shown below in Table A - 2.The 8015 supports two interrupt priority levels: low and high. The nature of the interrupt mechanism is very standard and thus, a low level interrupt service routine can only be interrupted by a high level interrupt a

47、nd a high level interrupt service routine cannot be interrupted.Interrupt SourceVector AddressPower On Reset0000HExternal Interrupt 00003HTimer 0 Overflow000BHExternal Interrupt 10013HTimer 1 Overflow001BHSerial Receive/Transmit0023HTimer 2 Overflow002BHTable A - 2Interrupt Priority RegisterEach int

48、errupt source can be individually set to one of two priority levels by altering the value of the IP (Interrupt Priority) SFR. If an interrupt sources corresponding bit in this register is set, it will have high priority. Similarly, if the corresponding bit is cleared the interrupt will be of low priority and subject to being interrupted by any high priority interrupts.Interrupt Enable RegisterAll interrupts are enabled or blocked by setting or clearing the EA bit (Enable All) of the IE (Interrupt Enable) register. Each interr