Hardware and Computer Organization毕业论文外文资料翻译.doc

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1、外文资料Hardware and Computer Organization From: Hardware and Computer Organization, Arnold S.BergerFigure 6.21is an excerpt form te data sheet for an SDRAM memory device from Micron Technology,Inc, a semiconductor memory manufacturer located in Boise ,ID.The timing diagram is for the MT48LC128MXAfamily

2、 of SDRAM memories.The devices are 513 Mbit parts organized as 4,8or 16-bit wide data paths . The Xis a placeholder for the organization (4,8or 16 bit wide).Thus ,the MT48LC128M4A2 32m* is organized as 32M*4,while the MT48LC128M4A2is organized as 8M*16.These devices are far more complicated in their

3、 operation then the simple SRAM memories weve looked at so far. However ,we can see the fundamental brust behavior in Figure 6.21.The fields marked COMMAND ,ADDRESS and DQ are represented as band of data,rather than individual bits .This is a simplification that allows us to show a group of signals

4、,such as 14address bits ,without having to show the state of each individual signal.The band is used to show where the signal must be stable and where it is allowed to chang .Notice how the signals are all synchronized to the rising edge of the clock .Once the READ command is issued and the address

5、is provided for where the burst is to originate ,there is a two clock cycle latency an sequentially stored data in the chip will then be available on every successive clock cycle.Clearly,this is far more efficient then reading one byte at a time .When we consider cache memories in greater detail,wel

6、l see that the on-chip caches are also designed to be filled from external memory in bursts of data.Thus ,we incur a penalty in having to set-up the initial conditions for the data transfer from external memory to the on-chip caches,but once the data transfer parameters are loaded ,the memory to mem

7、ory data transfer can take place quite rapidly.For this family of devices the data transfer takes place at a maximum clock rate of 133MHz.Newer SDRAM devices, called double data rate,or DDR chips,can transfer data on both the rising and falling edges of the clock .Thus ,a DDR chip with a 133 MHz clo

8、ck input can transfer data at a speedy 266MHZ.These parts are designated ,for reasons unknown,as PC2700 devices .Any SDRAM chip capable of conforming to a 266MHZ clock rate are PC2700.Modern DRAM design takes many different forms.Weve been discussing SDRAM because this is the most common form of DRA

9、M in a modern PC.Your graphics card contains video DRAM.Older PCs contained extended data out ,or EDO DRAM.Today ,the most common type of SDRAM is DDR SDRAM .The amazing thing about all of this is the incredibly low cost of this type of memory .At this writing (summer of 2004),you can purchase 512 M

10、bytes of SDRAM for about 10 cents per megabyte .A memory with the same capacity ,built in static RAM would cost well over 2,000.Memory -to -Processor Interface The last typic that well tackle in this chapter involves the details of how the memory system and the processor communicate with each other

11、.Admittedly ,we can only scratch the surface because there are so many variation on a theme when there are over 300 commercially available microprocessor families in the world today ,but lets try to take general overview without getting too deeply enmeshed in individual differences .In general, most

12、 microprocessor-based systems contain three major bus groupings :Address bus :A unidirectional bus from the process out memory .Data bus : A bi-directional bus carrying data from memory to the processor during read operations and from the processor to memory during write operations.Status bus : A he

13、terogeneous bus comprised of the various control and housekeeping signals need to coordinate t operation of the processor,its memory and other peripheral devices .Typical status bus signal include :a. RESETb. interrupt management c. clock signalsd. read and write signalse. read and write signalsThis

14、 is shown schematically in Figure 6.22 for the Motorola MC68000 processor .The 68000 has a 24-bit address bus and a 16-bit external data bus .However ,internally ,both address and data can be up to 32 bits in length.Well discuss the interrupt system and bus management system later on in this section

15、.The Data Bus is also homogeneous, but it is bidirectional.Data goes out from memory to the processor on a read operation and from the processor to memory on a write operation, Thus, data can flow in either direction , depending upon the instruction being executed.The Status Bus is heterogeneous.It

16、is made up of different kinds of signal,so we cant group the some are bidirectional.The Status Bus is the “housekeeping”bus.All of the signals that are also needed to control system operation are grouped into the Status Bus.Lets now look at how the signals on these buses work together with memory so

17、 that we may read and write.Figure 6.23 shows us the processor side of the memory interface.Now we can see how the processor and the clock work together to sequence the accessing of the memory data.While it may seem quite bewildering at fires .It is actually many additional signals that may present

18、or absent in various processor designs and tried to restrict our discussion to the bare essentials .The Y-axis shows the various signals coming from the processor.In order to simplify things ,weve grouped all the signals for the address bus and the data bus into a “band”of signals.That way ,at any g

19、iven time ,we can assume that some are 1 and some are 0,but the key is that we must specify when they are valid.The crossings,or Xs in the address and data buses may be changing ,such as an address changing to a new value,or data coming from the processor .Since the microprocessor is a state machine

20、,everything is synchronized with the edges of the clock.Some events occur on the positive going edges and some may be synchronized with the negative going edges .Also.for convenience.well divide the bus cycles into identifiable time signatures called T states.” Not all processors work this way ,but

21、this is a reasonable approximation of how may processors actually work.Keep in mind that the processor is always running these bus cycles.These operations form it Fundamental method of data exchange between the processor and memory.Therefore ,we can answer a question that was posed at the beginning

22、of this chapter.Recall that the state machine truth table for the operation ,ADD B,A left out any explanation of how the data got into the registers in the first place.and how the instruction itself got into the computer.Thus, before we look at the timing diagram for the processor/memory interface,

23、we need to remind ourselves that the control of this interface is handled by another part of our state machine.In algo-rithmic terms,we do a “function call”to the portion of the state machine that handles the memory interface,and the data is read or written by that algorithm.Lets start with a READ c

24、ycle .During the falling edge of the clock in T1the address becomes stable and the ADDR VLA signal is asserted LOW.Also ,the RD signal goes LOW to indicate that this is a read operation .During the falling edge of T3 the READ and ADDRESS VALID signals are de-asserted indicating to memory that that t

25、he cycle is ending and the data from memory is being read by the processor.Thus ,the memory must be able to provide the data to the processor within two full clock cycles(all of T2 plus half of T1 and half of T3).Suppose the memory isnt fast enough to guarantee that the data will be ready in time.We

26、 discussed this situation for the case of the NEC static RAM chip and decided that a possible solution would be to slow the processor clock until the access time requirements for the memory could be guaranteed to be within specs.Now we will consider another alternative.In this scenario,the memory sy

27、stem may assert the WAIT signal back to the processor.The processor checks the state of the WAIT signal on the on the falling edge of the clock during T2cycle.If the WAIT sinnal is asserted ,the processor generates another T2 cycle and checks again.As long as the WAIT signal is LOW,the processor kee

28、ps marking time in T2,Only when WAIT goes high will the processor complete the bus cycle.This is called a wait state ,and is used to synchronize slower memory to faster processors .The write cycle is similar to the read cycle.During the falling edge of the clock in T1 the address becomes valid.Durin

29、g the rising edge of the clock in T2 the data to be written is put on the data bus and the write signal goes low,indicating a memory write operation .WATI signal has the same function in T2 on the write cycle.During the falling edge of the clock in T3 the WRsignal is de-asserted ,giving the memory a

30、 rising edge to store the data .ADDR VAL also is de-asserted and the write cycle ends .There are several interesting concepts buried in the previous discussion that require some explanation before we move on .The first is the idea of a state machine that operates on both edges of the clock.so lets c

31、onsider that first .When we input single clock signal to the processor in order to synchronize tis internal operations,we dont really see what happens to the internal clock .Many processors will internally convert te clock to a 2-phase clock .A timing diagram for a 2-phase clock is shown in Figure 6

32、.24.The input clock ,which is generated by an external oscillator ,is converted to a 2-phase clock,labeled 1 and 2 .The two clock phases now 180 degrees out of phase from each other,so that every rising or falling edge of the CLKIN signal generates an internal rising clock edge.How could we generate

33、 a 2-phase clock?You actually already know how to do it, but theres a piece of information that we first need to place in context.Figure 6.25 is a circuit that can be used to generate a 2-phase clock .The 4 XOR gates are convenient to use because there is a common integrated circuit part which conta

34、ins 4 Xor gates in one package.The circuit makes use of the propagation delays that are inherent in a logic gate .Suppose that each XOR gate has a propagation delay of 10ns .Assume that the clock input is LOW.One input of XOR gates 1 through 3 is permanently ties to ground (logic LOW).Since both inp

35、uts of gate 1 are LOW ,tis output is also LOW.This situation carries through to gates 2,3and 4.Now ,the CLKIN input goes to logic state HIGH.The output of gate 4goeshigh 10ns later and toggles the D-FF to change state.Since the Qand Q outputs are opposite each other,we conveniently have a source of

36、two alternationg clock phases by nature of the divide-by-two wiring of the D-FF.After a propagation delay of 30ns the output of tate 3 also goes HIGH,which causes the output of XOR gate 4 to go LOW again because the output of an XOR gate is LOW if both inputs are the same and HIGH if the inputs are

37、different .At some time later,the clock input goes low again and we generate nother 30ns wide positive going pulse at the output of gate 4 because for 30ns both outputs are different .This cause the D-FF to toggle at both edges of the clock and the Q and Q outputs give us the alternating phases that

38、 we need.Figure6.26 shows the relevant waveforms .This circuit works for any clock frequency that has a period greater than 4 XOR gate delays .Also ,by using both outputs of the D-FF,we are guaranteed a two-phase clock output that is exactly 180 degrees out of phase from each other.Now we can revisi

39、t Figure6.23 and see the other subtle point that was buried in the diagram.Since we are apparently changing states on the rising and falling edges of the clock ,we now know that the internal state machine of the processor is actually using a 2-phase clock and each of the Tstates is ,in reality,two s

40、tates.Thus ,we can redraw the timing diagram for a READ cycle as a state diagram.This will clearly demonstrate the READ phase of the bus cycle,represent as a state diagram.Referring to Figure 6.27 we can clearly see that in state T20the processor tests the state of the WAIT input.If the input is ass

41、erted LOW ,the processor remains in state T20 ,effectively lengthening the total time for the bus cycle.The advantage of the wait state over decreasing the clock frequency is that we can design our system such that a wait penalty is incurred only when the processor accesses certain memory regions,ra

42、ther than slowing it for all operations.We can now summarize the entire bus READ cycle as follows.T10: READ cycle begins.Processor outputs new memory address for READ operation .T11: Address is now stable and ADVAL goes LOWRD goes low indicating that a READ cycle is beginning T20: READ cycle continu

43、es.T21: Process samples WAIT input .If asserted T21 cycle continues.T30: READ cycle continues.T31: READ cycles terminates.ADVAL and RD are de-asserted and processor inputs the data form memory .Direct Memory Access(DMA)Well conclude Chapter 6with a brief discussion of another form of memory access c

44、alled DMA,or direct memory access.The need for a DMA system is a result of the fact that memory system and the processor are connected to each other by buses.Since the bus is the only path in and out of the system.conflicts will arise when peripheral devices,such as disk drives or network cards have

45、 data for the processor,but the processor is busy executing program code .In many systems, the peripheral devices and memory share the same buses with the processor .When a device,such as a hard disk drive needs to transfer data to the processor,we could imagine two scenarios .Scenario 11Disk drive:

46、“Sorry for the interrupt boss,Ive got 512 bytes for you.”2Processor:“Thats a big 10-4little disk buddy.Gimme the first byte.”3Disk drive:“Sure boss.Here it is. “4Processor:“Got it,Gimme the next one”5Disk drive:“Here it is .”Repeat steps 4 and 510 more times.1Disk drive:“Yo boss,I got 512 bytes and

47、theyre burning a hole in my platter.I gotta go ,I gotta to .”(BBUS REQUEST)2Processor:“OK,ok pipe down lemme finish this instruction and Ill get off the bus.OK,Im done ,the bus is yours ,and dont dawdle,Im busy .”(BUS GRANT)3Disk drive:“Thanks boss ,Youre a pal .I owe you one ,Ive got it ,”(BUS ACKN

48、OWLEDGE)4Disk drive:“Ill put the data in the usual spot.”(Said to itself)5Disk drive:“Hey boss!Wake up ,Im off the bus.”6Processor:Thanks disk ,Ill retriever the data from the usual spot7Disk drive:“10-4,The usual spot,Im off.”As you might gather from these two scenarios ,the second was more efficie

49、nt because the peripheral device,the hard disk,was able to take over memory control from the processor and write all of its data in a single burst of activity .The processor had placed its memory interface in a tri-state condition and was waiting for the signal from the disk drive that it could return to the bus .Thus the DMA allows other devices to take over control of the buses