2022年锁相技术译文翻译 .pdf

《2022年锁相技术译文翻译 .pdf》由会员分享，可在线阅读，更多相关《2022年锁相技术译文翻译 .pdf（13页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、锁相技术译文翻译英文原名：An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI 译文：45 纳米 SOI 全数字片上测量电路表征锁相环响应特性名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 13 页 - - - - - - - - - 第 2 页 /共 13 页English 中文An On-Chip All-Digital Me

2、asurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI Dennis Fischette, Richard DeSantis, and John Haeseon Lee Advanced Micro Devices, Inc., Sunnyvale, CA 94085-3905 USA AbstractAn all-digital measurement circuit, built in 45-nm SOI-CMOS enables on-chip characterization of phase-

3、locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circuit can be used to plot step-response vs. time, measure static phase error, and observe phase-lock status. INTRODUCTION Many applications such as PCI Exp

4、ress ? require a PLL to produce a low-jitter clock at a given frequency while meeting stringent bandwidth and jitter peaking requirements. Process, voltage, and temperature (PVT) variations as well as random device mismatch make it difficult to guarantee a narrow range for PLL response. For example,

5、 loop parameters such as VCO gain could vary by more than 2X over PVT corners. In Fig. 1, we see the closed-loop jitter transfer functions of two PLLs with identical reference clock and output frequencies. One PLL exhibits large peaking and low bandwidth while the other shows little peaking but high

6、 bandwidth. Although differences in this example are more extreme than usual, similar but smaller differences often result from PVT variations. 45 纳米 SOI 全数字片上测量电路表征锁相环响应特性作者信息摘要 全数字化测量电路，45 纳米SOI-CMOS工艺使其能够片上表征锁相环（PLL）对自诱导相步进的响应。这种技术允许估计PLL 闭环带宽和抖动峰值。该电路可用于绘制阶跃响应随时间变化的曲线， 测量静态相位误差，并观察相位锁定状态。导言许多应用像

7、PCI Express? 需要一个PLL产生一个低抖动额定频率时钟的同时满足精确带宽和抖动峰值的要求。工艺， 电压和温度（ PVT ）的变化与器件选用随机性一样会造成失配，使其难以确保PLL的窄带响应。 例如，环路参数如VCO增益变化可能超过PVT角 2 倍上以。图1 中，我们看到两个具有相同参考时钟和输出频率 PLL 的闭环抖动传递函数。一个 PLL展现出大峰值和窄带宽，而另一个则是小峰值宽带宽。 虽然这个例子中显示的差异比通常所见要极端，这种相似而差异的特性往往会因PVT变化而变小。名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - -

8、 - 名师精心整理 - - - - - - - 第 2 页，共 13 页 - - - - - - - - - 第 3 页 /共 13 页PLL response is often measured on a test bench using signal generators, oscilloscopes, and/or spectrum analyzers. For example, the transfer functions in Fig. 1 were automatically generated by modulating the 100-MHz reference clock w

9、ith various frequencies while observing the amplitudes of the resulting output spurs. Such methods, which may require many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to characterize PLL response 1-3. Fig. 2 shows the PLL output phase transien

10、t response to an induced phase step. Similar to other second-order feedback systems, the PLL tends to overcorrect (or overshoot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring several times before settling to its final lock state. A

11、key metric in the PLL step-response is crossover, defined here as the elapsed time from input step to onset of phase overshoot. Another key metric is MaxOvershoot. It measures the maximum overcorrection in the step response. PLL 响应往往是通过一个使用信号发生器、示波器、和/ 或频谱分析仪组成的试验台来测试的。例如， 图 1 中，传递函数是通过调制100MHz能产生各种

12、频率的参考时钟， 同时观察输出马刺产生的幅值自动生成的。 这样的方法， 可能需要若干秒才能完成， 使得对更快、 更便宜方法需求更为迫切， 而最好的方法便是通过片上技术来表征锁相环响应特性1-3。图 2显示了 PLL对致相步进响应的输出瞬态相位。 类似于其他二阶反馈系统，锁相环往往因其工作是消除相位误差而趋于过调 （或过调） 。如果 PLL 工作在欠阻尼状态， 比如在这个例子中，环锁相环可能在其到达最终时钟状态前，经过几次锁定。锁相环阶跃响应的一个关键指标是交叉反应， 在此定义为从输入步进到相位超调开始出现所用的时间。另一个关键指标是最大超调量。 它可以测量阶跃响应的最大过调量。名师资料总结 -

13、 - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 3 页，共 13 页 - - - - - - - - - 第 4 页 /共 13 页Transient simulations and closed-form loop equations 4 show that crossover is inversely proportional to the PLLs 3dB closed-loop bandwidth; the smaller crossover is, the higher the bandw

14、idth (Fig. 3). Notice that crossover is largely independent of the size of the phase step. Both simulations and loop equations also predict that MaxOvershoot is proportional to the maximum peaking in the closed-loop transfer function; the larger MaxOvershoot is, the greater the peaking (Fig. 4). Not

15、ice that the magnitude of the overshoot is also proportional to the input step size. These relationships between time- and frequency-domain behaviors allow us to make fast time-domain measurements and then relate the results back to frequency-domain performance specifications. The circuit 瞬态模拟和闭环回路方

16、程4 表明，交叉反应和 PLL 的 3dB闭环带宽成反比； 交叉反应越小，带宽越大（图3）。请注意，交叉反应在很大程度上与相位步长无关。模拟和回路方程还预测到闭环传递函数中最大超调与最大峰值是成正比的; 最大超调越大，峰值越高（图4）。请注意，超调幅度也正比于输入步长。时域和频域的这种特性让我们能够进行快速时域测量， 然后将这些结果关联到频域性能指标中。本文呈现的电路实现显示，PLL 阶跃响应可能被全数字化片上有限状态机捕获，从而实现快速表征锁相名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - -

17、 - 第 4 页，共 13 页 - - - - - - - - - 第 5 页 /共 13 页implementation presented in this paper shows that the PLL step response may be captured by an all-digital, on-chip finite state machine, allowing for fast PLL characterization. Silicon results indicate that this circuit could allow for Power-on calibrat

18、ion of the PLL bandwidth and peaking for compensation of process variations. CIRCUIT DESIGN The PLL under test (Fig. 5) is a standard integer-N charge-pump PLL. The only modification is the addition of loop measurement circuitry. The feedback divisor (N) is programmable from 5 to 63 although N=8 dur

19、ing loop measurement tests. The charge-pump current, loop-filter resistance, and VCO gain are programmable to allow for bandwidth and peaking adjustments as well as jitter optimization. The PLL bandwidth may be configured from 3 to 25 MHz while the peaking may be varied from 4 dB. The VCO operates f

20、rom 1.6 to 5 GHz. The expected reference clock frequency range is 100 to 200 MHz. 环。硅的实验效果表明，该电路可以让PLL 带宽和峰值的电校准工艺变化得到弥补。电路设计被测 PLL（图 5）是一个标准的整数N 电荷泵锁相环。 唯一的修改就是增加了回路测量电路。反馈除数（N）是由 5 至 63可编程的， 虽然在回路测量试验中N=8。电荷泵电流、 循环过滤电阻和VCO增益可编程，以允许带宽和峰值的调整以及抖动的优化。 PLL 带宽可配置为3 到 25MHz ，而峰值可在1 至 4 分贝之间变化。VCO操作频率范围为1

21、.6 到 5GHz 。预期的参考时钟频率范围为100 至 20MHz 。名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 5 页，共 13 页 - - - - - - - - - 第 6 页 /共 13 页A simple way to induce the required input phase step is to flip the polarity of the reference clock so its phase is advanced by half a clock c

22、ycle. A disadvantage to this approach is that the magnitude of the phase step is dependent on the reference clock duty cycle. This is undesirable because overshoot tests require a large and predictable input phase step. Instead, the circuit implementation presented here manipulates the feedback divi

23、sor to induce a known phase step. The circuit then automatically measures the resulting crossover and MaxOvershoot. Fig.6 shows a block diagram of the loop measurement test circuit. It includes three main units: control, crossover detector, and MaxOvershoot detector. The control unit contains two sy

24、nchronizers (to VCO clock), three edge detectors (rising and falling), and logic to enable the induced phase step. The crossover detector includes a bang-bang phase detector, a phase-error change-of-sign detector, and a 10-bit counter. The MaxOvershoot detector contains a feedback count sampler, a c

25、omparator, and a maximum overshoot register. 一个简单的诱发所需输入相位的方法是翻转极性参考时钟使其相位提前半个时钟周期。 这种方法的一个缺点是，相步距大小与参考时钟占空比有关。这是不可取的，因为超调测试需要一个大且可预见输入相位步进。 相反，这里呈现的电路通过操作诱导反馈除数来诱导已知相位步进。该电路将自动测试产生的交叉反应和最大超调量。 图 6 显示了一个环路测量测试电路的框图。 它包括三个主要单元：控制模块、 交叉反应检测器，和最大超调探测器。控制单元包含两个（对VCO时钟的）同步器， 三个（上升和下降） 边沿探测器，和使能致相一步的逻辑。交叉

26、反应检测器包括一个快速相器检测器，一个相位误差符号变化探测器和一个10 位计数器。该最大超调探测器包含一个反馈计数采样器， 一个比较器， 和一个最大超调寄存器。名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 6 页，共 13 页 - - - - - - - - - 第 7 页 /共 13 页Fig. 7 gives an example of how the input phase step is generated. The PLL is initially locked with

27、 N=8. When the StepEnb signal is asserted, N=11 is loaded into the incrementing feedback divider. One feedback clock cycle later, StepEnb is de-asserted and N is reset to the default value of 8. This process has the effect of delaying the feedback clock (FbClk) by 3 VCO clock cycles and instantaneou

28、sly introducing a known phase error. At this point, the PLL begins to react to the induced phase error by increasing the VCO frequency. At the first rising RefClk after the phase step is applied, the BwEnb signal asserts to enable the crossover-time counter (BwCnt9:0) and begin the crossover-time me

29、asurement (Fig. 8). The bang-bang phase detector (BBPD) samples the 图 7 给出了一个输入相位步进如何形成的例子。 PLL 最初以 N=8锁定。 当 StepEnb信号有效时， N=11装入递增反馈分频器。一个反馈时钟周期后期，StepEnb 被撤销并且 N复位到默认值8。这一进程会造成反馈时钟（ FbClk ）拖延 3 个 VCO 时钟周期和瞬间引入一个已知的相位误差。因此，PLL 开始通过增加锁相环VCO的频率对诱导相位误差作出反应。第一阶段在应用相位步进之后RefClk 上升，BwEnb信号保持以使能交叉反应时间计数器

30、（BwCnt9:0 ），并开始交叉反应时间测量（图8）。该快速相位比较器（BBPD ） 采样每一个上升RefClk 的 FbClk值。信号BBPD1和 BBPD2 是 BBPD 移出的名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 7 页，共 13 页 - - - - - - - - - 第 8 页 /共 13 页FbClk level at every rising RefClk. Signals BBPD1 and BBPD2 are shifted versions of BB

31、PD; they operate in the VCO clock domain and are updated once every reference clock cycle by the Load_BBPD signal. The state indicates that the PLL has eliminated the induced phase error and that FbClk is now leading RefClk. The BwValid signal is set, halting the crossover-time counter and completin

32、g the crossover-time measurement. The 10-bit BwCnt value is converted to time with Whereis the nominal VCO clock period and K is the induced step size in VCO clock cycles. K must be subtracted from the measurement results because the phase step causes the PLL to produce K additional VCO cycles durin

33、g the re-lock process. When the BwValid signal is asserted, the maximum overshoot test begins (Fig. 9). In the overshoot test, the internal state of the Feedback divider (FbCnt 5:0) is sampled at every RefRise pulse where RefRise is a synchronized (to VCO) version of the rising edge of RefClk. RefCl

34、k is not used directly to sample the feedback divider count because it is not synchronous with the VCO clock. The sampled feedback divider count is placed in the SmplCnt 5:0 register. During initial phase overshoot, the 情形， 它们工作在VCO的时钟域内， 并通过 Load_BBPD信号立即更新每个参考时钟周期。这种状态表明， PLL 已经消除锁相环相位误差，FbClk 则正引

35、导RefClk 。BwValid 信号置位，停止交叉反应时间计数器，完成交叉反应时间的测量。通过以下关系10 位BwCnt 值转换为时间公式其中是压控振荡器的标称时钟周期，K是 VCO时钟周期引起的步长。K 必须被减于测量结果， 因为在重锁过程中相步进会使 PLL 产生 K的额外 VCO 周期。当 BwValid 信号有效时， 最大超调测试开始（图 9）。在超调测试中，内部反馈分频器（ FbCnt 5:0）的状态是在每一个RefRise 脉冲采样的，其中RefRise 是RefClk 上升沿同步（以振荡器）样本。RefClk 不能直接用于采样反馈分频器计数值， 因为它与VCO时钟不同步。 采样

36、的反馈分频计数值存放在SmplCnt 5:0寄存器中。在初始超调阶段，VCO加快， FbClk 领先名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 8 页，共 13 页 - - - - - - - - - 第 9 页 /共 13 页VCO speeds up, FbClk pulls ahead of RefClk, and the sampled feedback divider count increases in value. A circuit compares SmplCn

37、t 5:0 to the previous maximum overshoot (MaxOvershoot 5:0). If SmplCnt 5:0 is greater than MaxOvershoot 5:0, then the UpdateOS signal is asserted and SmplCnt 5:0 replaces MaxOvershoot 5:0 at the next rising edge of RefFall, which is analogous to the aforementioned RefRise signal. Eventually, the VCO

38、 slows down and the sampled feedback divider count moves back toward zero. If the PLL exhibits ringing, then the sampled feedback divider count may continue past zero (undershoot) and begin recording values such as N-1, N-2, N-3, etc. To filter these undershoot counts, the comparator ignores any Smp

39、lCnt 5:0 values greater than N/2. The RefClk synchronizer latency must be subtracted from the measured MaxOvershoot count to calculate the actual maximum Overshoot. The synchronizer latency in VCO clock cycles (Nsync) is measured in another test mode where FbCnt 5:0 is sampled by RefRise as previous

40、ly described but no phase step is applied. The MaxOvershoot value measured in VCO cycles is converted to time using The precision of the overshoot detector is ref/N, and so the measurement is less precise 于 REFCLK ，采样的反馈分频器计数值增加。通过一个电路比较SmplCnt 5:0与上一个最大超调量（最大超调量 5:0）。如果 SmplCnt5:0大于最大超调量5:0，则 Updat

41、eOS信号有效并且SmplCnt 5:0取代下次RefFall的上升沿，这同上述的RefRise 信号类似。最终， VCO减缓，采样反馈分频器计数器置零。 如果 PLL 起振， 那么采样反馈分频器计数可能会持续过零（负脉冲） 并开始记录数值如N-1、N-2、N-3 等。为了过滤这些负冲计数值，比较器会忽略任何比N/2 大的 SmplCnt5:0值。RefClk 的同步延迟值必须被减于测量的最大超调计数值来计算实际的最大超调量。 VCO时钟周期（ Nsync）的同步延迟是在另一个测试模式下测量的，其中FbCnt5:0是如前所述RefRise 抽样而没有应用相步进的。VCO周期测量的最大过冲值通过

42、下式转换为使用的时间公式该超调探测器的精度为ref/N ，所以小反馈因子的测试不太精确。在生成输入相步名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 9 页，共 13 页 - - - - - - - - - 第 10 页/共 13 页with small feedback divisors. In generating the input phase step, the feedback clock may be advanced instead of retarded. This

43、allows for a larger phase step in cases in which the nominal feedback divisor is close to the maximum value of 63. A potential downside of advancing FbClk is that phase Overshoots smaller than the RefClk synchronizer latency cannot be detected. These step-response algorithms require that the PLL sta

44、tic phase error is less than the maximum overshoot. If not true, the required phase error sign-change does not occur, the bandwidth counter saturates at its maximum value, and the BwValid bit remains low. If the static phase error is large, then the FbClk phase can be advanced, forcing a phase error

45、 sign-change. The resolution of the bandwidth test is one reference clock period, and so the measurement becomes less precise as the PLL bandwidth Approaches the reference clock frequency. The loop measurement circuit can also be used to generate a Time-trend of the PLL step-response, similar to a T

46、IE plot. Instead of automatically detecting and the feedback divider count is captured after exactly N reference clock cycles. By varying N from 1 to the maximum value of 63, the PLL step response may be plotted vs. time, as in Fig. 2. The loop measurement circuit may be used as a lock detector by r

47、epeatedly measuring. If it does not vary, then the PLL is locked. The static phase error may be estimated by comparing the measuredto the expected synchronizer latency of 1-2 VCO cycles. By default, all loop measurement clocks are gated when not in use to minimize power. All flip-flops are of the 进时

48、， 反馈时钟可能提前而不是滞后。这允许了一个反馈因子接近最大值63 的较大相步进产生。 FbClk 提前的一个潜在缺点是，超调量小于RefClk同步器的延迟无法检测出来。这些步进响应算法要求PLL 静态相位误差小于最大超调量。如果不是这样的话，需要的相位误差符号变化不会出现，带宽计数器达到最大值而饱和，而BwValid位仍然为低。 如果静态相位误差较大，则FbClk 相位可能被提前，迫使相位误差符号变化。 带宽测试的解决方法是一个参考时钟周期， 因此测量因PLL 带宽接近参考时钟频率而变得不那么精确。回路测试电路也可用于生成PLL 阶跃响应的时间趋势图，类似于 TIE 图。反馈分频器计数值会在

49、N 个参考时钟周期后被精确捕获，而不是自动检测和最大超调量。 通过从 1 到最大值63 改变 N，PLL 阶跃响应可以用于绘制随时间变化的曲线，如图2。回路测试电路通过反复测量作为一个锁探测器。如果不改变， 那么 PLL 被锁定。 静态相位误差可通过比较测量的和预期的1-2VCO周期的同步延迟来确定。默认情况下， 所有回路测量时钟在不使用时将设置门限以减小功率。 所有触发器都是感性放大器以便快速启动时间和快速解决亚稳定信号。名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 10 页，共

50、 13 页 - - - - - - - - - 第 11 页/共 13 页sense-amplifier type for fast setup time and fast resolution of meta-stable signals. EXPERIMENTAL RESULTS While the loop measurement circuit has been successfully used with a wide range of PLL frequencies, the experimental results presented here focus on a PLL op