2022年ADDA等一些芯片的verilog程序[参 .pdf

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1、/* AD0809 module v1.0 work up to 5M sample = 25us 40khz for normal clk = 2.5M sample = 30us 33khz */ module ad0809( clkin, adclk, eoc, st, ale, datain, oe, dataout ); input clkin; input eoc; input 7:0datain; output st; output ale; output oe; output adclk; output 7:0dataout; reg adclk; reg 7:0dataout

2、; reg st; reg oe; reg ale; /frequence divider for AD parameter Div_adclk = 8d9;/(9+1)*2=20 adclk=2.5M parameter Div_clk_state = 4d4;/(4+1)*2=10 clk_state=5M 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 20 页 - - - - - - - - - reg 8:0div_cnt_ad;/frequence div c

3、nt reg 3:0div_cnt_state; reg clk_state; always(negedge clkin)begin if(div_cnt_ad != Div_adclk) div_cnt_ad = div_cnt_ad + 1b1; else begin div_cnt_ad = 0; adclk = adclk; end if(div_cnt_state != Div_clk_state) div_cnt_state = div_cnt_state + 1b1; else begin div_cnt_state = 0; clk_state = clk_state; end

4、 end /*AD convert*/ reg 3:0state; reg 7:0delay; initial begin state = 4d0; end always(negedge clk_state)begin case(state) 4d0:begin /clear all st = 1b0; oe = 1b0; ale = 1b0; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 2 页，共 20 页 - - - - - - - - - delay = 8h00; sta

5、te = 4d1; end 4d1:begin /ale latch ale = 1b1; state = 4d2; end 4d2:begin /st rasing st = 1b1; state = 4d3; end 4d3:begin /ale falling ale = 1b0; state = 4d4; end 4d4:begin /st falling st = 1b0; state = 4d5; end 4d5:begin/eoc delay after st; 8clock+2us = 26stata_clk delay = delay + 1b1; if(delay = 8d

6、26) state = 4d6; else state = 4d5; end 4d6:begin /test eoc(convete finished); if(eoc) state = 4d7; else state = 4d6; end 4d7:begin /out enable oe = 1b1; state = 4d8; end 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 3 页，共 20 页 - - - - - - - - - 4d8:begin /take data

7、dataout = datain; state = 4d9; end 4d9:begin /out unable; return oe = 1b0; state = 4d0; end default: state = 4d0; endcase end endmodule /* clk = 5Mhz T = 0.2us the distance = 0.2 * 1000_000 * data *340m/s */ module chao (clk, start ,reset, trig, echo,data,success,time_out); input clk,start,reset,ech

8、o; output trig,data,success,time_out; reg trig,time_out,success; reg 31:0data; reg 3:0state; parameter Prepare = 4d1; parameter Delay_trig = 4d2; parameter Echo_raising = 4d3; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 4 页，共 20 页 - - - - - - - - - parameter Echo_

9、falling = 4d4; parameter Time_out = 4d5; parameter Success = 4d6; reg 7:0dely; /60*0.2=12us reg 31:0timer; /if timer is bigger than 0 x1e848 (far than 4.0 m),time out always(negedge clk or negedge reset)begin if(!reset)begin state = Prepare; end else begin case(state) Prepare:begin timer = 32h0000_0

10、000; trig = 1b0; /success = 1b0; /time_out = 1b0; if(!start)begin trig = 1b1;/trig the device dely = 8b0000_0000; state = Delay_trig; end else begin state = Prepare; end end Delay_trig:begin /delay 12us dely = dely + 1b1; if(dely != 8d60)begin /60 state = Delay_trig; 名师资料总结 - - -精品资料欢迎下载 - - - - - -

11、 - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 5 页，共 20 页 - - - - - - - - - end else begin trig = 1b0; /end of trig state = Echo_raising; end end Echo_raising:begin /wait for echo rassing timer = timer + 1b1; if(echo)begin timer = 32d0;state = Echo_falling; end else begin state = 32d2250)begin/450u

12、s timer = 32d0; state = Prepare; end else begin if(echo)begin timer = 32d0;state = Echo_falling; end else begin state = Echo_raising; end end*/ end Echo_falling:begin /wait for echo falling or timeouttimer = 32d120000)begin /out of 10m state = Time_out; end else begin if(!echo)begin data = timer;sta

13、te = Success;end else begin state = Echo_falling; end end end 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 6 页，共 20 页 - - - - - - - - - Time_out:begin time_out = time_out; state = Prepare; end Success:begin success = success; state = Prepare; end default:begin stat

14、e = Prepare; end endcase end/end of if end endmodule /* clk = 5Mhz T = 0.2us the distance = 0.2 * 1000_000 * data *340m/s */ module chao (clk, start ,reset, trig, echo,data,success,time_out); input clk,start,reset,echo; output trig,data,success,time_out; reg trig,time_out,success; reg 31:0data; reg

15、3:0state; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 7 页，共 20 页 - - - - - - - - - parameter Prepare = 4d1; parameter Delay_trig = 4d2; parameter Echo_raising = 4d3; parameter Echo_falling = 4d4; parameter Time_out = 4d5; parameter Success = 4d6; reg 7:0dely; /60*

16、0.2=12us reg 31:0timer; /if timer is bigger than 0 x1e848 (far than 4.0 m),time out always(negedge clk or negedge reset)begin if(!reset)begin state = Prepare; end else begin case(state) Prepare:begin timer = 32h0000_0000; trig = 1b0; /success = 1b0; /time_out = 1b0; if(!start)begin trig = 1b1;/trig

17、the device dely = 8b0000_0000; state = Delay_trig; end else begin state = Prepare; end end Delay_trig:begin /delay 12us 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 8 页，共 20 页 - - - - - - - - - dely = dely + 1b1; if(dely != 8d60)begin /60 state = Delay_trig; end el

18、se begin trig = 1b0; /end of trig state = Echo_raising; end end Echo_raising:begin /wait for echo rassing timer = timer + 1b1; if(echo)begin timer = 32d0;state = Echo_falling; end else begin state = 32d2250)begin/450us timer = 32d0; state = Prepare; end else begin if(echo)begin timer = 32d0;state =

19、Echo_falling; end else begin state = Echo_raising; end end*/ end Echo_falling:begin /wait for echo falling or timeouttimer = 32d120000)begin /out of 10m state = Time_out; end else begin if(!echo)begin data = timer;state = Success;end else begin state = Echo_falling; end end end 名师资料总结 - - -精品资料欢迎下载

20、- - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 9 页，共 20 页 - - - - - - - - - Time_out:begin time_out = time_out; state = Prepare; end Success:begin success = success; state = Prepare; end default:begin state = Prepare; end endcase end/end of if end endmodule /* max358 modlule v1.0 sclk =

21、25M convert = 0.588M 2010/8/10 */ module max538 ( clk, databus, din, sclk, cs 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 10 页，共 20 页 - - - - - - - - - ); /*direction*/ input clk; output din; output sclk; output cs; input 15:0databus; /*attribute*/ reg din; reg sc

22、lk; reg cs; /*inner*/ reg 15:0datatemp; reg 7:0state; reg 3:0cnt16; reg 3:0delay; /*state define*/ parameter Prepare = 8d1; parameter Cs_0 = 8d2; parameter Cs_1 = 8d4; parameter Sclk_1 = 8d8; parameter Sclk_0 = 8d16; parameter Delay = 8d32; always(negedge clk)begin case(state) Prepare:begin/clear cs

23、 = 1b1; sclk = 1b0; cnt16 = 4b0000; delay = 4b0000; datatemp = databus; state = Cs_0; end 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 11 页，共 20 页 - - - - - - - - - Cs_0:begin cs = 1b0;/select the chip din = datatemp15;/offer data first state = Sclk_1; end Sclk_1:b

24、egin sclk = 1b1; /raising take the data datatemp = datatemp 1; /shift left state = Sclk_0; end Sclk_0:begin sclk = 1b0; /falling din = datatemp15;/offer data cnt16 = cnt16 + 4b0001; if(cnt163 & cnt162 & cnt161 & cnt160)begin/16 state = Delay; end else state = Sclk_1; end Delay:begin delay = delay +

25、4b0001; cs = 1; if(delay3)state = Prepare; else state = Delay; end default: state = Prepare; endcase end endmodule a/* 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 12 页，共 20 页 - - - - - - - - - tlc1549 v1.4 adclk = 0.333M sample = 20K 2011/8/9 */ module tlc1549 ( r

26、eset, clk50M, adclk, adcs, addata, databus ); /* direction define */ input reset; input clk50M; input addata; output adclk; output adcs; output databus; /* attribute */ reg adclk; reg adcs; reg 15:0databus;/ 输出数据/inner register reg 15:0datatmp;/ 暂存数据reg 3:0cnt;/ 计数器统计十位reg 9:0state;/ 状态热码reg 3:0dela

27、y;/conveter delay counter parameter Adcs_1 = 10d1; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 13 页，共 20 页 - - - - - - - - - parameter Adcs_0 = 10d2; parameter Clear = 10d4; parameter Convert_1= 10d8; parameter Convert_0= 10d16; parameter Finish = 10d32; parameter

28、 Reset = 10d64; parameter Delay = 10d128; parameter Waitdata = 10d256; parameter Div = 8d24;/div = (24+1)*2=50 fre = 50M/50 = 1M;adclk = 0.333M reg 7:0div_cnt;/frequence div cnt reg clkbuf; wire clkin; /frequence divide always(negedge clk50M)begin if(div_cnt != Div) div_cnt = div_cnt + 1; else div_c

29、nt = 0; end always(negedge clk50M)begin if(div_cnt = 0) clkbuf = clkbuf; end assign clkin = clkbuf; /ad convert always(negedge clkin)begin case(state) Adcs_1:/stop I/O clock begin adcs = 1; state = Adcs_0; end Adcs_0:/enable contrl begin adcs = 0; state = Clear; end 名师资料总结 - - -精品资料欢迎下载 - - - - - -

30、- - - - - - - - - - - - 名师精心整理 - - - - - - - 第 14 页，共 20 页 - - - - - - - - - Clear:/clear the temp data begin datatmp = 16h0000; cnt = 0; delay = 0; adclk = 1b1; state = Convert_0; end Convert_0: begin adclk = 1b0;/falling edge datatmp = datatmp1; state = Waitdata; end Waitdata: begin if(addata) dat

31、atmp0 = 1;/this is inportant state = Convert_1; end Convert_1: begin if(!reset) state = Reset; else begin cnt = cnt + 1b1; if(cnt3 & cnt0)begin databus = datatmp&16h3fff;/take the data adclk = 1b1;/rasing edge state = Finish; end else begin adclk = 1b1;/rasing edge state = Convert_0; end end end 名师资

32、料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 15 页，共 20 页 - - - - - - - - - Finish: begin adcs = 1; state = Delay; end Delay: begin delay = delay + 1; if(delay3 & delay2)/1100 state = Reset; else state = Delay; end Reset: begin state = Adcs_1; end default: state = Rese

33、t; endcase end endmodule /clk 为 16 倍波特频率。/外部可在E 的下降沿读走接收到数据的sbuff ，在下次数据来时，E 会置 1。module uartrec(clk,e,rx,sbuff); input clk,rx; output 7:0 sbuff; output e; reg e; reg 7:0 sbuff; assign rx2 = rx; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 16 页，共 20 页 - - - - - - -

34、 - - initial begin state=0; e=1; end parameter Start = 8b0000_0001; parameter S_f = 8b0000_0010; parameter S_b = 8b0000_0100; /inner singnal reg 9:0 sbuff_tmp;/10bit mode reg 8:0 state; reg 8:0delay; reg 3:0bits; always(negedge clk)begin case(state) Start:begin e = 1b1; if(!rx)begin /wait for start

35、bit delay = 8d0; bits = 4d0; sbuff_tmp = 10d0; state = S_f; end else state = Start; end S_f:begin delay = delay + 8d1; if(delay = 8d7)begin sbuff_tmp 1; if(rx) sbuff_tmp9=1b1; else sbuff_tmp9=1b0; state = S_f; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 17 页，共 20

36、页 - - - - - - - - - end else if(delay = 8d15)begin delay = 8d0; bits = bits + 4d1; if(bits = 4d9)begin bits = 4d0; e = 1b0; state = S_b; end end else state = S_f; end S_b:begin e = 1b0; sbuff = sbuff_tmp8:1; state = Start; /stop end default:state = Start; endcase end endmodule /clk 为 16 倍波特频率。/E 下降锁

37、存数据sbuff 开始发送 ,busy=0,忙/发送完后， busy 置 1。module uartsend(clk,e,sbuff,tx,busy); input clk; reg 7:0 count; input 7:0 sbuff; reg 7:0 buff; input e; output busy; reg busy; output tx; reg tx; reg 2:0 state; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 18 页，共 20 页 - - - -

38、- - - - - initial begin state=0; tx=1; busy=1; end always(negedge clk) begin count=count+1; case(state) 0: begin if(e=0) begin state=1; count=0; buff=sbuff; tx=0; /start 0; busy=0; end end 1: begin if(count3:0=15) begin if(count7:4=4b1000)begin state=3; tx=1; /end 1 end else begin state=2; if(buff&8

39、b1)tx=1; else tx=0; end end end 2: begin buff1; state=1; end 3: begin if(count3:0=15)begin busy=1; if(e)state=0; else state=3; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 19 页，共 20 页 - - - - - - - - - end end default:state=0; endcase end endmodule 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 20 页，共 20 页 - - - - - - - - -