keil调试环境下S3C2440.s的分析.doc

《keil调试环境下S3C2440.s的分析.doc》由会员分享，可在线阅读，更多相关《keil调试环境下S3C2440.s的分析.doc（19页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、如有侵权，请联系网站删除，仅供学习与交流keil调试环境下S3C2440.s的分析【精品文档】第 19 页; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs ;向量中断模式/非向量中断模式设置;通过PSRs（程序状态寄存器）来设置; 系统工作模式设定; CPSR是当系统前程序状态寄存器，SPSR是备份程序状态寄存器。其中CPSR共用一个物理寄存器，而SPSR一共有5个物理寄存器; CPSR寄存器设定：CPSR4.0 为M4-M0，通过它可以设定处理器的工作模式Mode_USR EQU 0x10 ; 用户

2、模式Mode_FIQ EQU 0x11 ; 快速中断模式Mode_IRQ EQU 0x12 ; 外部中断模式Mode_SVC EQU 0x13 ; 超级用户模式Mode_ABT EQU 0x17 ; 数据访问终止模式Mode_UND EQU 0x1B ; 未定义指令终止模式Mode_SYS EQU 0x1F ; 系统模式I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 外部中断屏蔽位，置1，关闭中断，置0，打开中断F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 快速中断屏蔽位，置1，关

3、闭中断，置0，打开中断;- Stack and Heap Definitions -;/ Stack Configuration (Stack Sizes in Bytes);/ Undefined Mode ;/ Supervisor Mode ;/ Abort Mode ;/ Fast Interrupt Mode ;/ Interrupt Mode ;/ User/System Mode ;/ ; 栈配置，系统的栈空间设定UND_Stack_Size EQU 0x00000000 ; 未定义模式的栈大小SVC_Stack_Size EQU 0x00000008 ; 超级用户模式的栈大小A

4、BT_Stack_Size EQU 0x00000000 ; 数据访问终止模式的栈大小FIQ_Stack_Size EQU 0x00000000 ; 快速中断模式的栈大小IRQ_Stack_Size EQU 0x00000080 ; 外部中断模式的栈大小USR_Stack_Size EQU 0x00000400 ; 用户模式的栈大小ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) ; 所有模式的堆栈相加得到总堆栈的大小; ARM的汇编程序

5、由段组成，段是相对独立的指令或数据单位，每个段由AREA伪指令定义，并定义段的属性。-READWRITE（读写）、READONLY（只读） AREA STACK, NOINIT, READWRITE, ALIGN=3 ; 开辟一个堆栈段，段名字为STACK，定义为可读可写，; 不初始化内存单元，或将内存单元初始化为0Stack_Mem SPACE USR_Stack_Size ; _initial_sp SPACE ISR_Stack_Size ; 汇编代码的地址标号Stack_Top ; 堆栈段内容结束， 在这里放个标号,用来获得堆栈顶部地址;/ Heap Configuration;/ H

6、eap Size (in Bytes) ;/ Heap_Size EQU 0x00000000 ; 堆大小设置 AREA HEAP, NOINIT, READWRITE, ALIGN=3 ; 开辟一个段，名字为HEAP可读可写，不初始化内存单元，或者初始化为0_heap_baseHeap_Mem SPACE Heap_Size_heap_limit;- Memory Definitions -; Internal Memory Base Addresses ; 片上SRAM的基地址，即内存基地址IRAM_BASE EQU 0x40000000;- Watchdog Timer Definiti

7、ons -WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address 看门狗定时器基地址WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset 看门狗控制寄存器偏移地址，相对于基址WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset 看门狗数据寄存器偏移地址，相对于基址WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset 看门狗计数寄存器偏移地址，相对于基址;/ W

8、atchdog Timer Setup;/ Watchdog Timer Control Register (WTCON);/ Prescaler Value ;/ Watchdog Timer Enable;/ Clock Division Factor;/ 16 32 64 128;/ Interrupt Generation Enable;/ Reset Enable;/ ;/ Watchdog Timer Data Register (WTDAT);/ Count Reload Value ;/ ;/ Watchdog Timer SetupWT_SETUP EQU 1 ; 看门狗设置

9、WTCON_Val EQU 0x00000000 ; 看门狗控制寄存器设置，关闭看门狗WTDAT_Val EQU 0x00008000 ; 看门狗数据寄存器设置，初始值即为0x8000;- Clock and Power Management Definitions -CLOCK_BASE EQU 0x4C000000 ; Clock Base Address ; 时钟基地址LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset ; 锁相环锁定时间计数寄存器偏移地址，相对于基址MPLLCON_OFS EQU 0x04 ; MPLL

10、 Configuration Register Offset ; MPLL配置寄存器偏移地址，相对于基址，主时钟源PLLUPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset ; UPLL配置寄存器偏移地址，相对于基址，USB时钟源PLLCLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset ; 时钟控制寄存器偏移地址，相对于基址CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset ; 时钟减慢控制寄存器偏移地址，相

11、对于基址CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset ; 时钟分频器控制寄存器偏移地址，相对于基址CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset ; 摄像头时钟分频器控制寄存器偏移地址，相对于基址，UPLL提供;/ Clock Setup;/ PLL Lock Time Count Register (LOCKTIME);/ U_LTIME: UPLL Lock Time Count Value for UCLK ;/ M_LTIME: MPLL

12、Lock Time Count Value for FCLK, HCLK and PCLK ;/ ;/ MPLL Configuration Register (MPLLCON);/ MPLL = (2 * m * Fin) / (p * 2s);/ m: Main Divider m Value ;/ m = MDIV + 8;/ p: Pre-divider p Value ;/ p = PDIV + 2;/ s: Post Divider s Value ;/ s = SDIV ;/ ;/ UPLL Configuration Register (UPLLCON);/ UPLL = (

13、m * Fin) / (p * 2s);/ m: Main Divider m Value ;/ m = MDIV + 8;/ p: Pre-divider p Value ;/ p = PDIV + 2;/ s: Post Divider s Value ;/ s = SDIV ;/ ;/ Clock Generation Control Register (CLKCON);/ AC97 Enable;/ Camera Enable;/ SPI Enable;/ IIS Enable;/ IIC Enable;/ ADC + Touch Screen Enable;/ RTC Enable;

14、/ GPIO Enable;/ UART2 Enable;/ UART1 Enable;/ UART0 Enable;/ SDI Enable;/ PWMTIMER Enable;/ USB Device Enable;/ USB Host Enable;/ LCDC Enable;/ NAND FLASH Controller Enable;/ SLEEP Enable;/ IDLE BIT Enable;/ ;/ Clock Slow Control Register (CLKSLOW);/ UCLK_ON: UCLK ON;/ MPLL_OFF: Turn off PLL;/ SLOW_

15、BIT: Slow Mode Enable;/ SLOW_VAL: Slow Clock Divider ;/ ;/ Clock Divider Control Register (CLKDIVN);/ DIVN_UPLL: UCLK Select;/ UCLK = UPLL clock;/ UCLK = UPLL clock / 2;/ HDIVN: HCLK Select;/ HCLK = FCLK;/ HCLK = FCLK / 2;/ HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8;/ HCLK =

16、FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6;/ PDIVN: PCLK Select;/ PCLK = HCLK;/ PCLK = HCLK / 2;/ ;/ Camera Clock Divider Control Register (CAMDIVN);/ DVS_EN: ARM Core Clock Select;/ ARM core runs at FCLK;/ ARM core runs at HCLK;/ HCLK4_HALF: HDIVN Division Rate Change Bit;/ If HDIV

17、N = 2 in CLKDIVN then HCLK = FCLK / 4;/ If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8;/ HCLK3_HALF: HDIVN Division Rate Change Bit;/ If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3;/ If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6;/ CAMCLK Select;/ CAMCLK = UPLL;/ CAMCLK = UPLL / CAMCLK_DIV;/ CAMCLK_DIV: C

18、AMCLK Divider ;/ Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1);/ Divider is used only if CAMCLK_SEL = 1;/ ;/ Clock SetupCLOCK_SETUP EQU 0 ; 时钟设置LOCKTIME_Val EQU 0x0FFF0FFF ; PLL锁定时间计数器值MPLLCON_Val EQU 0x00043011 ; MPLL配置寄存器值UPLLCON_Val EQU 0x00038021 ; UPLL配置寄存器值CLKCON_Val EQU 0x001FFFF0 ; 时钟配置寄存器值CLK

19、SLOW_Val EQU 0x00000004 ; 时钟减慢控制寄存器值CLKDIVN_Val EQU 0x0000000F ; 时钟分频控制寄存器值CAMDIVN_Val EQU 0x00000000 ; 摄像头分频控制寄存器值;- Memory Controller Definitions -; 存储控制器设置MC_BASE EQU 0x48000000 ; Memory Controller Base Address ; 存储控制器基地址BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset ; 总线宽度和等待控制寄存器BA

20、NKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset ; BANK0-BOOT ROM控制寄存器设置BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset ; BANK1BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset ; BANK2BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset ; BANK3BANKCON4_OFS EQU 0x14 ; Bank 4 Control

21、 Register Offset ; BANK4BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset ; BANK5BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset ; BANK6BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset ; BANK7REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset ; DRAM/SDRAM刷新控制BANKSIZE_OFS

22、EQU 0x28 ; Flexible Bank Size Register Offset ; 可调的bank大小寄存器MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset ; 模式控制寄存器bank6MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset ; 模式控制寄存器bank7;/ Memory Controller Setup;/ Bus Width and Wait Control Register (BWSCON);/ ST7: Use UB/LB for Bank 7;/ WS7: Ena

23、ble Wait Status for Bank 7;/ DW7: Data Bus Width for Bank 7;/ 8-bit 16-bit 32-bit Reserved;/ ST6: Use UB/LB for Bank 6;/ WS6: Enable Wait Status for Bank 6;/ DW6: Data Bus Width for Bank 6;/ 8-bit 16-bit 32-bit Reserved;/ ST5: Use UB/LB for Bank 5;/ WS5: Enable Wait Status for Bank 5;/ DW5: Data Bus

24、 Width for Bank 5;/ 8-bit 16-bit 32-bit Reserved;/ ST4: Use UB/LB for Bank 4;/ WS4: Enable Wait Status for Bank 4;/ DW4: Data Bus Width for Bank 4;/ 8-bit 16-bit 32-bit Reserved;/ ST3: Use UB/LB for Bank 3;/ WS3: Enable Wait Status for Bank 3;/ DW3: Data Bus Width for Bank 3;/ 8-bit 16-bit 32-bit Re

25、served;/ ST2: Use UB/LB for Bank 2;/ WS2: Enable Wait Status for Bank 2;/ DW2: Data Bus Width for Bank 2;/ 8-bit 16-bit 32-bit Reserved;/ ST1: Use UB/LB for Bank 1;/ WS1: Enable Wait Status for Bank 1;/ DW1: Data Bus Width for Bank 1;/ 8-bit 16-bit 32-bit Reserved;/ DW0: Indicate Data Bus Width for

26、Bank 0;/ 16-bit 32-bit;/ ;/ Bank 0 Control Register (BANKCON0);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacc: Access Cycle;/ 1 clocks 2 clocks 3 clocks 4 clocks;/ 6 clocks 8 clo

27、cks 10 clocks 14 clocks;/ Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/ PMC: Page Mode Configuration;/ norma

28、l (1 data) 4 data 8 data 16 data;/ ;/ Bank 1 Control Register (BANKCON1);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacc: Access Cycle;/ 1 clocks 2 clocks 3 clocks 4 clocks;/ 6 cl

29、ocks 8 clocks 10 clocks 14 clocks;/ Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/ PMC: Page Mode Configurati

30、on;/ normal (1 data) 4 data 8 data 16 data;/ ;/ Bank 2 Control Register (BANKCON2);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacc: Access Cycle;/ 1 clocks 2 clocks 3 clocks 4 clo

31、cks;/ 6 clocks 8 clocks 10 clocks 14 clocks;/ Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/ PMC: Page Mode C

32、onfiguration;/ normal (1 data) 4 data 8 data 16 data;/ ;/ Bank 3 Control Register (BANKCON3);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tacc: Access Cycle;/ 1 clocks 2 clocks 3 clocks 4 clocks;/ 6 clocks 8 clocks 10 clocks 14 clocks;/ Tcoh: Chip Selection Hold Time after n