最新FPGA轨道交通自动售票电路.doc

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1、精品资料FPGA轨道交通自动售票电路.设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额5元，并支持找零。要求：（1）用状态机方法设计；（2）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综合。（3）将设计代码和仿真代码写在作业本上。module zhaoling(clock,reset,A,ticket,change); input clock,reset; input 2:0 A; output ticket; output 2:0 change; reg 2:0 state; reg ticket; reg 2:0 chang

2、e; parameter sta_0=3d0, sta_1=3d1, sta_2=3d2, sta_3=3d3, sta_4=3d4, sta_5=3d5; always (posedge clock or negedge reset) if(!reset) begin state=sta_0; ticket=0; change=0; end else case(state) sta_0:if(A = 1) begin state = sta_1; ticket=0; change=0; end else if(A = 2) begin state = sta_2; ticket=0; cha

3、nge=0; end else if(A = 5) begin state = sta_5; ticket=1; change=0; end else begin state = sta_0; ticket=0; change=0; end sta_1:if(A = 1) begin state = sta_2; ticket=0; change=0; end else if(A = 2) begin state = sta_3; ticket=0; change=0; end else if(A = 5) begin state = sta_0; ticket=1; change=1; en

4、d else begin state = sta_1; ticket=0; change=0; end sta_2:if(A = 1) begin state = sta_3; ticket=0; change=0; end else if(A = 2) begin state = sta_4; ticket=0; change=0; end else if(A = 5) begin state = sta_0; ticket=1; change=2; end else begin state = sta_2; ticket=0; change=0; end sta_3:if(A = 1) b

5、egin state = sta_4; ticket=0; change=0; end else if(A = 2) begin state = sta_5; ticket=1; change=0; end else if(A = 5) begin state = sta_5; ticket=1; change=3; end else begin state = sta_3; ticket=0; change=0; end sta_4:if(A = 1) begin state = sta_5; ticket=1; change=0; end else if(A = 2) begin stat

6、e = sta_5; ticket=1; change=1; end else if(A = 5) begin state = sta_5; ticket=1; change=4; end else begin state = sta_4; ticket=0; change=0; end sta_5:if(A = 1) begin state = sta_1; ticket=0; change=0; end else if(A = 2) begin state = sta_2; ticket=0; change=0; end else if(A = 5) begin state = sta_5

7、; ticket=1; change=0; end else begin state = sta_5; ticket=0; change=0; end default: state = sta_0; endcase endmoduletimescale 1ns/1ns module test; reg Clock,Reset; reg 2:0 A; wire Ticket; wire 2:0 Change; initial begin A=0; Reset = 1; Clock = 0; Reset = 0; #10 Reset = 1; end always #10 Clock=Clock;

8、 initial begin #20 A = 1; #20 A = 1; #20 A = 1; #20 A = 1; #20 A = 1; #20 A = 1; #20 A = 2; #20 A = 2; #20 A = 2; #20 A = 2; #20 A = 1; #20 A = 2; #20 A = 1; #20 A = 2; #20 A = 2; #20 A = 2; #20 A = 2; #20 A = 5; end zhaoling m(.clock(Clock),.reset(Reset),.A(A),.ticket(Ticket),.change(Change);endmodule