最新VHDL双语教学第2章(共21张PPT课件).pptx

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1、VHDLSimulation & Synthesis(Design Flow / Language Framework)第一页，共二十一页。AgendanBasic Language Framework第二页，共二十一页。Majority Voter CircuitnOutput 1 of there is more 1s than 0snOutput 0 of there is more 0s than 1s多数(dush)表决器第三页，共二十一页。SchematicCPLD第四页，共二十一页。VHDL Descriptionlibrary ieee;use ieee.std_logic_1

2、164.all;-entity XYZ is - Can put anything after the - port ( A1, A2, A3 : in std_logic; F : out std_logic );end XYZ;-architecture XYZ _arch of XYZ isbegin F = (A1 and A2) or (A2 and A3) or (A1 and A3); end XYZ_arch;ABCA1A2A3FA1A2A3FFileXYZ.VHD第五页，共二十一页。VHDL in Quartus第六页，共二十一页。Synthesis & Fit第七页，共二十

3、一页。Simulation第八页，共二十一页。Download to Chips第九页，共二十一页。Agenda第十页，共二十一页。XYZ Clock DiagramXYZ(Entity)ABCFXYZ_arch1(Architecture)第十一页，共二十一页。XYZ.VHD (1) data flowlibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is port ( A, B, C : in std_logic; - Comments F : out std_logic );end XYZ;-architecture XYZ_arc

4、h of XYZ isbegin F = (A and B) or (B and C) or (C and A); end XYZ_arch; 第十二页，共二十一页。XYZ.VHD (2) data flowlibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is port ( A, B, C : in std_logic; F : out std_logic );end XYZ;-architecture XYZ_arch of XYZ isbegin F = 1 when (A = 1) and (B = 1) else 1 when

5、(B = 1) and (C = 1) else 1 when (A = 1) and (C = 1) else 0;end XYZ_arch; 第十三页，共二十一页。XYZ.VHD (3) behaviorallibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is port ( A, B, C : in std_logic; F : out std_logic );end XYZ;-architecture XYZ_arch of XYZ isbegin process (A, B, C) begin if (A = 1) and (B

6、 = 1) then F = 1; elsif (B = 1) and (C = 1) then F = 1; elsif (A = 1) and (C = 1) then F = 1; else F = 0; end if; end process;end XYZ_arch;第十四页，共二十一页。XYZ.VHD (4) structurallibrary ieee;use ieee.std_logic_1164.all;library altera;use altera.maxplus2.ALL;-entity XYZ is port ( A, B, C : in std_logic; F

7、: out std_logic );end XYZ;-architecture XYZ_arch of XYZ is signal F1, F2, F3: std_logic;begin U1: and2 port map(A, C, F1); U2: and2 port map(A, B, F2); U3: and2 port map(B, C, F3); F = F1 or F2 or F3;end XYZ_arch; 第十五页，共二十一页。XYZ All in One Block DiagramXYZ(Entity)ABCFXYZ_arch1XYZ_arch2XYZ_arch3XYZ_a

8、rch4(Architecture)第十六页，共二十一页。XYZ.VHD (All in One)library ieee;use ieee.std_logic_1164.all;LIBRARY altera;USE altera.maxplus2.ALL;-*entity XYZ is port ( A, B, C : in std_logic; F : out std_logic );end XYZ;-*architecture XYZ_arch1 of XYZ isbegin F = (A and B) or (B and C) or (C and A);end XYZ_arch1;-a

9、rchitecture XYZ_arch2 of XYZ isbegin F = 1 when (A = 1) and (B = 1) else 1 when (B = 1) and (C = 1) else 1 when (A = 1) and (C = 1) else 0;end XYZ_arch2;-architecture XYZ_arch3 of XYZ isbegin process (A, B, C) begin if (A = 1) and (B = 1) then F = 1; elsif (B = 1) and (C = 1) then F = 1; elsif (A =

10、1) and (C = 1) then F = 1; else F = 0; end if; end process;end XYZ_arch3;-architecture XYZ_arch4 of XYZ is signal F1, F2, F3: std_logic;begin U1: and2 port map(A, C, F1); U2: and2 port map(A, B, F2); U3: and2 port map(B, C, F3); F = F1 or F2 or F3;end XYZ_arch4;-第十七页，共二十一页。 A B F C A B F C A1 B1 C1

11、A2 B2 C2 F1 F2 F XXYYZZ XXYYZZXYZ第十八页，共二十一页。MY_PACKAGE.VHDlibrary ieee;use ieee.std_logic_1164.all;-package my_package is component XYZ is port ( A, B, C : in std_logic; F : out std_logic ); end component;end my_package; 第十九页，共二十一页。XXYYZZ.VHDlibrary ieee;use ieee.std_logic_1164.all;library work;use

12、work.my_package.all;-entity XXYYZZ is port ( A1, A2, B1, B2, C1, C2 : in std_logic; F : out std_logic );end XXYYZZ;-architecture XXYYZZ_arch of XXYYZZ is signal F1, F2 : std_logic;begin G1: XYZ port map(A1, B1, C1, F1); G2: XYZ port map(A2, B2, C2, F2); F = F1 or F2; end XXYYZZ_arch;第二十页，共二十一页。内容(nirng)总结VHDL。F : out std_logic )。XYZ.VHD (1) data flow。F : out std_logic。XYZ.VHD (2) data flow。F = 1 when (A = 1) and (B = 1) else第二十一页，共二十一页。