2022年单片机_温度控制系统_外文翻译_外文文献_英文文献_中英翻译 .pdf

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1、1 Design of the Temperature Control System Based on AT89C51 ABSTRACT The principle and functions of the temperature control system based on micro controller AT89C51 are studied, and the temperature measurement unit consists of the 1-Wire bus digital temperature sensor DS18B20. The system can be expe

2、cted to detect the preset temperature, display time and save monitoring data. An alarm will be given by system if the temperature exceeds the upper and lower limit value of the temperature which can be set discretionarily and then automatic control is achieved, thus the temperature is achieved monit

3、oring intelligently within a certain range. Basing on principle of the system, it is easy to make a variety of other non-linear control systems so long as the software design is reasonably changed. The system has been proved to be accurate, reliable and satisfied through field practice. KEYWORDS: AT

4、89C51; micro controller; DS18B20; temperature 1 INTRODUCTION Temperature is a very important parameter in human life. In the modern society, temperature control (TC) is not only used in industrial production, but also widely used in other fields. With the improvement of the life quality, we can find

5、 the TC appliance in hotels, factories and home as well. And the trend that TC will better serve the whole society, so it is of great significance to measure and control the temperature. Based on the AT89C51 and temperature sensor DS18B20, this system controls the condition temperature intelligently

6、. The temperature can be set discretionarily within a certain range. The system can show the time on LCD, and save monitoring data; and automatically control the temperature when the condition temperature exceeds the upper and lower limit value. By doing so it is to keep the temperature unchanged. T

7、he system is of high anti-jamming, high control precision and flexible design; it also fits the rugged environment. It is mainly used in peoples life to improve the quality of the work and life. It is also versatile, so that it can be convenient to extend the use of the system. So the design is of p

8、rofound importance. The general design, hardware design and software design of the system are covered. 1.1 Introduction The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically 名师资料总结 - - -精品资料欢迎下载

9、 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 21 页 - - - - - - - - - 2 used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The auto

10、motive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power

11、-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integr

12、ated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti

13、-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive,

14、 as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage con

15、ditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers

16、and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device. 1.2 The AT89C51 provides the following standard features 4Kbytes of Flash, 128 bytes of RAM, 32 I/

17、O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple ser-ial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. T

18、he Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 2 页，共 21 页 - - - - - - - - - 3 RAM contents but freezes the osc

19、illator disabling all other chip functions until the next hardware reset. 1.3Pin Description VCC Supply voltage. GND Ground. Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used a

20、s high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program

21、verification. External pull ups are required during program verification. Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/so -urce four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be

22、 used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull ups

23、. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emit

24、s the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and durin

25、g accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also rece

26、ives the high-order address bits and some control signals durin Flash programming and verification. Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/sou -rce four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the in

27、ternal pull ups and can be used as inputs. As inputs, Port 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 3 页，共 21 页 - - - - - - - - - 4 3 pins that are externally being pulled low will source current (IIL) because of the pull ups. Port 3 also serves the functions of

28、 various special features of the AT89C51 as listed below: RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is

29、also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri-ng each access to external Data Memory. If

30、desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：Program

31、Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP：External Access Enable. EA must be s

32、trapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin alsreceives

33、 the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 ：Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 ： Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 an

34、d XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected whil

35、e XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 4 页，共 21 页 - - - - - - - - - 5 divide-by-tw

36、o flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions register

37、s remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the inter

38、nal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle sho

39、uld not be one that writes to a port pin or to external memory. Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mod

40、e is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabiliz

41、e. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. 2 Programming Algorithm Before programming the AT89C51, the address, data and control signals

42、should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control si

43、gnals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array

44、or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - -

45、 名师精心整理 - - - - - - - 第 5 页，共 21 页 - - - - - - - - - 6 datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. 2.1Ready/Busy: The progress of byte programming can

46、 also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY . Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read

47、back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. 2.2 Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals an

48、d by holding ALE/PROG low for 10 ms. The code array is written with all “1” s. The chip erase operation must be executed before the code memory can be re-programmed. 2.3 Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H,

49、and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming 2.4 Programming Interface Every code byte in th

50、e Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside